Sequential circuit with error detection
View Patent ↗Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
1. A chip comprising:
a datapath;
a sequential unit comprising a data output and a data input coupled to the datapath; and
a logic unit connected to the datapath at the data input of the sequential unit, the logic unit having a dynamic logic gate, wherein the logic unit to monitor a data arrival time on the datapath at the data input of the sequential unit, the logic unit to assert an error signal to cause an instruction to be re-executed, if the data arrival time is later than a predetermined time, wherein the sequential unit is located in the datapath to prevent the datapath metastability.
2. The chip of claim 1 , wherein the logic unit comprises a pulse generator coupled to the dynamic logic gate.
3. The chip of claim 2 , wherein the pulse generator comprises a delay unit and a comparing logic unit.
4. The chip of claim 3 , wherein the comparing logic unit is an Exclusive-OR (XOR) gate.
5. The chip of claim 1 , wherein the dynamic logic gate to receive a clock signal or a delayed version of the clock signal, and wherein the sequential logic unit also receives the clock signal.
6. The chip of claim 1 , wherein the dynamic logic gate is a dynamic inverter.
7. The chip of claim 1 , wherein the input is blocked from the output during a first clock phase and transparent to the output during a second clock phase.
8. The chip of claim 7 , wherein the dynamic logic unit to pre-charge during the first clock phase and to evaluate during the second clock phase.
9. The chip of claim 1 further comprises a pipe-line stage having the sequential unit.
10. The chip of claim 1 , wherein the sequential unit is one of:
a latch;
a master-slave flip-flop; or
a time borrowing latch.
11. A system comprising:
a memory unit;
a processor, coupled to the memory unit, the processor including:
a pipe-line stage comprising a datapath, and a latch comprising a data output and a data input coupled to the datapath;
a logic unit, connected to the datapath at the data input of the latch, the logic unit having a dynamic logic gate, wherein the logic unit to monitor a data arrival time on the datapath at the data input of the latch, the logic unit to assert an error signal to cause an instruction to be re-executed, if the data arrival time is later than a predetermined time, wherein the sequential unit is located in the datapath to prevent the datapath metastability; and
a wireless interface for allowing the processor to communicatively coupled to other devices.
12. The system of claim 11 , wherein the processor includes one or more processing cores.
13. The system of claim 11 , wherein the latch is a time borrowing latch.
14. The system of claim 11 , wherein the logic unit to detect a transition in data at the input during a clock phase when the latch is transparent.
15. The system of claim 11 , wherein the input is blocked from the output during a first clock phase and transparent to the output during a second clock phase.
16. The system of claim 15 , wherein the logic unit to pre-charge during the first clock phase and to evaluate during the second clock phase.
17. A chip comprising:
a time borrowing latch comprising a data output and a data input, the time borrowing latch positioned on a datapath in a pipeline stage; and
a logic unit, connected to the datapath at the data input of the time borrowing latch, the logic unit having a dynamic logic gate which in conjunction to other logic units to detect a transition in data to monitor a data arrival time on the datapath at the data input of the time borrowing latch during a clock phase, of a clock signal, when the time borrowing latch is transparent and to assert an error signal, if the data arrival time is later than a predetermined time, and wherein the sequential unit is located in the datapath to prevent the datapath metastability.
18. The chip of claim 17 , wherein the logic unit comprises a pulse generator coupled to the dynamic logic gate.
19. The chip of claim 18 , wherein the pulse generator comprises a delay unit and a comparing logic unit.
20. The chip of claim 17 , wherein the logic gate to receive the clock signal or a delayed version of the clock signal, and wherein the time borrowing latch also receives the clock signal.