IP Library Granted Patent US 8,872,355
Granted Patent B2
US 8,872,355 · App. 13/598,352 · Granted Oct 28, 2014

Semiconductor device with pre-molding chip bonding

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Quick Facts
Patent No.
US 8,872,355
App. No.
13/598,352
Granted
Oct 28, 2014
Kind
B2
Abstract

This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Claims (19)

1. A method of making a semiconductor device, comprising:

pressing an electrical contact of a chip into a bonding layer on a carrier;

curing the bonding layer, wherein the bonding layer, as cured, is coupled, at least in part, to the electrical contact;

applying a molding compound in contact with the chip and a first major surface of the bonding layer;

planarizing the bonding layer; then

coupling distribution circuitry to the electrical contact.

2. The method of claim 1 , wherein planarizing the bonding layer includes exposing a contact surface of the electrical contact, and wherein coupling the distribution circuitry couples the distribution circuitry to the contact surface.

3. The method of claim 2 , wherein planarizing the bonding layer includes planarizing the electrical contact to expose the contact surface of the electrical contact.

4. The method of claim 3 :

wherein the chip comprises a plurality of electrical contacts;

wherein pressing the electrical contact comprises pressing the plurality of electrical contacts into the bonding layer; and

wherein planarizing the electrical contact comprises planarizing the plurality of electrical contacts to make contact surfaces of the electrical contacts substantially co-planar.

5. A method of making a semiconductor device, comprising:

pressing an electrical contact of a chip into a bonding layer on a carrier;

curing the bonding layer, wherein the bonding layer, as cured, is coupled, at least in part, to the electrical contact;

applying a molding compound in contact with the chip and a first major surface of the bonding layer;

coupling distribution circuitry to the electrical contact; and

applying a buildup layer on a second major surface of the bonding layer opposite the first major surface and substantially surrounding the distribution circuitry.

6. The method of claim 5 , further comprising coupling solder bumps to the distribution circuitry, wherein the buildup layer secures, in part, the solder bumps.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2013
From: HU, CHUAN
To: INTEL CORPORATION
Reel/Frame 030780/0986 →