Transistor having tensile strained channel and system including same

1. A transistor structure comprising:

a substrate including a first layer comprising a first crystalline material;

a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material;

a capping layer formed on the tensile strained channel;

a film formed over the capping layer to impart strain to the tensile strained channel;

a metal gate on the capping layer;

a pair of sidewall spacers on opposite sides of the metal gate; and

a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

2. The transistor structure of claim 1 , wherein the first crystalline material comprises a III-V crystalline material, and the second crystalline material comprises one of Ge and SiGe.

3. The structure of claim 1 , further comprising a high-k layer formed on the tensile strained channel, wherein:

the metal gate is disposed on the high-k layer;

the channel is disposed between the first layer and the high-k layer.

4. The structure of claim 1 , wherein the channel, metal gate, spacers, source region and drain region are configured to define a multigate MOSFET.

5. The structure of claim 2 , wherein the tensile strained channel comprises one of a biaxially strained Ge material and a uniaxially strained SiGe material.

6. The structure of claim 5 , wherein the film has a lattice spacing that is smaller than the lattice spacing of the second crystalline material.

7. The structure of claim 2 , further including:

a upper wide bandgap layer between the tensile strained channel and the high-k dielectric Layers;

a lower wide bandgap layer between the tensile strained channel and the substrate.

8. The structure of claim 2 , wherein the capping layer comprises silicon.

9. The structure of claim 7 , further including:

a remote delta doped layer disposed between the upper wide bandgap spacer layer and the capping layer, or below the lower wide bandgap spacer layer, or both.

10. The structure of claim 1 , wherein the substrate further comprises:

a Si layer; and

a graded relaxed III-V buffer layer on the Si layer;

the first layer comprises a semi-insulating III-V epitaxially grown layer on the graded relaxed III-V buffer layer.

11. The structure of claim 2 , wherein the III-V crystalline material is from one of the Al group, the Ga/As/In group and the Ga/P/In group.

12. The structure of claim 2 , wherein the channel comprises a Ge material having a thickness be 1 ow about 300 Angstrom.

13. The structure of claim 2 , wherein the source region and the drain region both comprise a III-V semiconductor material.

14. A system comprising:

an electronic assembly comprising:

a transistor structure comprising:

a substrate including a first layer comprising a first crystalline material;

a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material;

a capping layer formed on the tensile strained channel;

a film formed over the capping layer to impart strain to the tensile strained channel;

a metal gate on the capping layer;

a pair of sidewall spacers on opposite sides of the metal gate; and

a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers; and

a main memory coupled to the transistor structure.

15. The system of claim 14 , wherein the first crystalline material comprises a III-V crystalline material, and the second crystalline material comprises one of Ge and SiGe.