Generic address scrambler for memory circuit test engine
View Patent ↗A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.
1. A memory device comprising:
a memory stack including one or more of coupled memory elements;
a built-in self-test circuit, the built-in self-test circuit including a generic programmable address scrambler for mapping of logical addresses to physical addresses for the memory elements; and
one or more registers to hold programming values for the generic programmable address scrambler;
wherein the generic programmable address scrambler includes a plurality of stages, a first stage of the plurality of stages including a first plurality of multiplexers to receive a logical address, the first stage to remap a plurality of elements of the logical address to produce a first plurality of values.
2. The memory device of claim 1 , wherein the one or more registers are to hold values to program the generic programmable address scrambler for a particular memory element.
3. The memory device of claim 1 , wherein the one or more registers include a first set of program values as selection values for the first set of multiplexers.
4. The memory device of claim 1 , wherein a second stage of the plurality of stages includes a second plurality of multiplexers to receive values of the first plurality of values, the second set of multiplexers to be programmed to perform functions of logic gates.
5. The memory device of claim 4 , wherein the one or more registers include a plurality of lookup values for each of the second plurality of multiplexers.
6. The memory device of claim 4 , wherein a third stage of the plurality of stages includes a third set of multiplexers, each of the second set of multiplexers being switchable to bypass the operation of the second plurality of multiplexers.
7. A logic element for a memory device comprising:
a memory controller for a memory stack of the memory device;
a built-in self-test circuit, the built-in self-test circuit including a generic programmable address scrambler for mapping for logical addresses to physical addresses for the memory stack; and
a configuration register to hold programming values for the generic programmable address scrambler;
wherein the generic programmable address scrambler includes a plurality of stages, a first stage of the plurality of stages including a first plurality of multiplexers to receive a logical address, the first stage to remap a plurality of elements of the logical address to produce a first plurality of values.
8. The logic element of claim 7 , wherein a second stage of the plurality of stages includes a second plurality of multiplexers to receive values of the first plurality of values, the second set of multiplexers to be programmed to perform functions of logic gates.
9. The logic element of claim 8 , wherein a third stage of the plurality of stages includes a third set of multiplexers, each of the second set of multiplexers being switchable to bypass the operation of the second plurality of multiplexers.
10. A system including;
a bus to connect elements of the system;
a processor coupled with the bus to process data for the system;
a transmitter to transmit data, a receiver to receive data, or both;
an omnidirectional antenna for data transmission, data reception or both; and
memory coupled to the bus to hold data for processing by the processor, the memory including a stacked memory device, the stack memory device including:
a memory stack including one or more of coupled memory elements,
a built-in self-test circuit, the built-in self-test circuit including a generic programmable address scrambler for mapping for logical addresses to physical addresses for the memory elements, and
one or more registers to hold programming values for the generic programmable address scrambler;
wherein the generic programmable address scrambler includes a plurality of stages, a first stage of the plurality of stages including a first plurality of multiplexers to receive a logical address, the first stage to remap a plurality of elements of the logical address to produce a first plurality of values.
11. The system of claim 10 , wherein the one or more registers are to hold values to program the generic programmable address scrambler for a particular memory element.
12. The system of claim 10 , wherein the one or more registers include a first set of program values as selection values for the first set of multiplexers.
13. The system of claim 10 , wherein a second stage of the plurality of stages includes a second plurality of multiplexers to receive values of the first plurality of values, the second set of multiplexer to be programmed to perform functions of logic gates.
14. The system of claim 13 , wherein the one or more registers include a plurality of lookup values for each of the second plurality of multiplexers.
15. The system of claim 13 , wherein a third stage of the plurality of stages includes a third set of multiplexers, each of the second set of multiplexers being switchable to bypass the operation of the second plurality of multiplexers.
16. The system of claim 10 , wherein the system is a computing system.
17. The system of claim 10 , wherein the system is a tablet computer.