IP Library Granted Patent US 8,431,438
Granted Patent B2
US 8,431,438 · App. 12/755,183 · Granted Apr 30, 2013

Forming in-situ micro-feature structures with coreless packages

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Quick Facts
Patent No.
US 8,431,438
App. No.
12/755,183
Granted
Apr 30, 2013
Kind
B2
Abstract

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Claims (24)

1. A method comprising;

forming a cavity in a carrier material;

attaching a die in the cavity;

forming a dielectric material adjacent the die;

forming vias in a region of the dielectric material adjacent the die;

forming vias in the die area to expose die pads on the die;

forming die pad interconnect structures in the die area; and

patterning the carrier material to form at least one micro-feature structure.

2. The method of claim 1 further comprising wherein the at least one micro-feature structure comprises at least one of a heat spreader, a PoP land structure, and an inductor structure.

3. The method of claim 1 further comprising wherein the die is partially embedded into the coreless substrate, and wherein the dielectric material is formed along a portion of a sidewall of the die.

4. The method of claim 1 further comprising wherein the die comprises a portion of a coreless bumpless build-up layer package.

5. The method of claim 1 wherein patterning the carrier material comprises patterning the carrier material while the carrier material is disposed on the die.

6. The method of claim 1 further comprising wherein the carrier material comprises a first layer and a second layer separated by an etch stop layer, and wherein the micro-feature structure comprises the carrier material disposed on the etch stop layer that is disposed on the die.

7. The method of claim 2 further comprising wherein the carrier material comprises copper.

8. The method of claim 1 further comprising wherein the die comprising the micro-feature structure comprises a portion of a coreless, bumpless, build up layer package.

9. A method comprising;

attaching a die to a carrier material;

forming dielectric material surrounding the die;

forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure; and

patterning the carrier material to form micro-feature structures on the package structure.

10. Theo method of claim 9 further comprising forming die interconnect structures in the dielectric material.

11. The method of claim 9 further comprising wherein the carrier material comprises a first layer and a second layer separated by an etch top layer, wherein the first layer is removed, and the second layer that is disposed on the etch stop layer that is disposed on the die is patterned to form a heat spreader.

12. The method of claim 9 wherein the carrier material comprises a multi-layer separated by an etch stop layer.

13. The method of claim 9 further comprising wherein carrier material is patterned to form at least one of a PoP land structure and an inductor structure in a non-die region of the package structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2013
From: NALLA, RAVI K; MANUSHAROW, MATHEW J
To: INTEL CORPORATION
Reel/Frame 029601/0982 →