Strained channel region transistors employing source and drain stressors and systems including the same
View Patent ↗Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.
1. A device comprising:
a substrate comprising a source and a drain region, wherein the source and the drain region comprise a doped III-V compound semiconductor material wherein the doped III-V compound semiconductor material comprises one or more elements from group III of the periodic table and one or more elements from group V of the periodic table,
a channel region between the source and the drain region wherein a first end of the channel region abuts the source region and a second end of the channel region abuts the drain region wherein the doped III-V compound semiconductor material of the source and the drain regions creates strain in the channel region, and
a gate dielectric material disposed on three sides of the channel region and a gate electrode material disposed on the gate dielectric.
2. The device of claim 1 wherein the channel region comprises germanium.
3. The device of claim 1 wherein the channel region comprises a combination of germanium and silicon or a combination of germanium, silicon, and tin.
4. The device of claim 1 wherein the channel region comprises silicon.
5. The device of claim 1 wherein the one or more elements from group III of the periodic table are selected from the group consisting of B, Al, Ga, and In, and the one or more elements from group V of the periodic table are selected from the group consisting of P, As, and Sb.
6. The device of claim 1 wherein the source and the drain region comprise Al x In 1−x P, wherein 0.5<x<0.8, Ga x In 1−x P, wherein 0.5<x<0.8, GaSb x P 1−x , wherein 0.1<x<0.3, AlSb x P 1−x , wherein 0.1<x<0.3, AlAs x P 1−x , wherein 0.5<x<1, or GaAs x P 1−x , where 0.5<x<1.
7. The device of claim 1 wherein the source and the drain region comprise Al x In 1−x P, wherein x is between 0.2 and 0.5, Ga x In 1−x P, wherein x is between 0.2 and 0.5, Ga x In 1−x As, wherein x is between 0.7 and 1, Al x In 1−x P, wherein x is between 0.7 and 1, GaSb x P 1−x , wherein x is between 0.3 and 0.5, AlSb x P 1−x , wherein x is between 0.3 and 0.5, GaAs x Sb 1−x , wherein x is between 0.75 and 1, or AlAs x Sb 1−x , wherein x is between 0.75 and 1.
8. The device of claim 1 wherein the channel region is tensely strained.
9. The device of claim 1 wherein the channel region is compressively strained.
10. The device of claim 1 wherein the source and drain regions are doped with germanium, carbon, silicon, magnesium, beryllium, manganese, or zinc.
11. A computing device comprising:
a motherboard;
a communication chip mounted on the motherboard; and
a processor mounted on the motherboard, the processor comprising a transistor, the transistor comprising:
a substrate comprising a source and a drain region, wherein the source and the drain region comprise a III-V compound semiconductor material, wherein the III-V compound semiconductor material comprises one or more elements from group III of the periodic table and one or more elements from group V of the periodic table,
a channel region between the source and the drain region wherein a first end of the channel region abuts the source region and a second end of the channel region abuts the drain region wherein the doped III-V compound semiconductor material of the source and the drain regions creates strain in the channel region, and
a gate dielectric material disposed on three sides of the channel region and a gate electrode material disposed on the gate dielectric.
12. The device of claim 11 wherein the one or more elements from group III of the periodic table are selected from the group consisting of B, Al, Ga, and In, and the one or more elements from group V of the periodic table are selected from the group consisting of P, As, and Sb.
13. The device of claim 11 wherein the source and the drain region comprise Al x In 1−x P, wherein 0.5<x<0.8, Ga x In 1−x P, wherein 0.5<x<0.8, GaSb x P 1−x , wherein 0.1<x<0.3, AlSb x P 1−x , wherein 0.1<x<0.3, AlAs x P 1−x , wherein 0.5<x<1, or GaAs x P 1−x , where 0.5<x<1.
14. The device of claim 11 wherein the source and the drain region comprise Al x In 1−x P, wherein x is between 0.2 and 0.5, Ga x In 1−x P, wherein x is between 0.2 and 0.5, Ga x In 1−x As, wherein x is between 0.7 and 1, Al x In 1−x P, wherein x is between 0.7 and 1, GaSb x P 1−x , wherein x is between 0.3 and 0.5, AlSb x P 1−x , wherein x is between 0.3 and 0.5, GaAs x Sb 1−x , wherein x is between 0.75 and 1, or AlAs x Sb 1−x , wherein x is between 0.75 and 1.
15. A device comprising:
a substrate comprising a source and a drain region, wherein the source and the drain region comprise Al x In 1−x P, wherein 0.5<x<0.8, Ga x In 1−x P, wherein 0.5<x<0.8, GaSb x P 1−x , wherein 0.1<x<0.3, AlSb x P 1−x , wherein 0.1<x<0.3, AlAs x P 1−x , wherein 0.5<x<1, or GaAs x P 1−x , where 0.5<x<1,
a channel region between the source and the drain region wherein a first end of the channel region abuts the source region and a second end of the channel region abuts the drain region, and
a gate dielectric material disposed on three sides of the channel region and a gate electrode material disposed on the gate dielectric.
16. The device of claim 15 wherein the channel region comprises germanium.
17. The device of claim 15 wherein the channel region comprises a combination of germanium and silicon or a combination of germanium, silicon, and tin.
18. The device of claim 15 wherein the channel region comprises silicon.
19. The device of claim 15 wherein the channel region is tensely strained.
20. The device of claim 15 wherein the source and drain regions are doped with germanium, carbon, silicon, magnesium, beryllium, manganese, or zinc.
21. A device comprising:
a substrate comprising a source and a drain region, wherein the source and the drain region comprise Al x In 1−x P, wherein x is between 0.2 and 0.5, Ga x In 1−x P, wherein x is between 0.2 and 0.5, Ga x In 1−x As, wherein x is between 0.7 and 1, Al x In 1−x P, wherein x is between 0.7 and 1, GaSb x P 1−x , wherein x is between 0.3 and 0.5, AlSb x P 1−x , wherein x is between 0.3 and 0.5, GaAs x Sb 1−x , wherein x is between 0.75 and 1, or AlAs x Sb 1−x , wherein x is between 0.75 and 1,
a channel region between the source and the drain region wherein a first end of the channel region abuts the source region and a second end of the channel region abuts the drain region, and
a gate dielectric material disposed on three sides of the channel region and a gate electrode material disposed on the gate dielectric.
22. The device of claim 21 wherein the channel region comprises germanium.
23. The device of claim 21 wherein the channel region comprises a combination of germanium and silicon or a combination of germanium, silicon, and tin.
24. The device of claim 21 wherein the channel region comprises silicon.
25. The device of claim 21 wherein the channel region is compressively strained.
26. The device of claim 21 wherein the source and drain regions are doped with germanium, carbon, silicon, magnesium, beryllium, manganese, or zinc.