Capacitor, method of increasing a capacitance area of same, and system containing same

1. A method of increasing a capacitance area of a tri-gate memory cell, where the tri-gate memory cell comprises a substrate, a first electrically insulating layer over the substrate, and a tri-gate capacitor and a tri-gate transistor over the first electrically insulating layer, and where the tri-gate capacitor has a first semiconducting fin, the method comprising:

depositing an inter-layer dielectric over the first electrically insulating layer and around the tri-gate capacitor and the tri-gate transistor, the inter-layer dielectric having an inter-layer dielectric surface;

forming a trench in the inter-layer dielectric in which at least a portion of the first semiconducting fin is exposed;

conformally depositing a first metal layer over the inter-layer dielectric surface, in the trench, and over the first semiconducting fin;

conformally depositing a second electrically insulating layer over the first metal layer;

conformally depositing a second metal layer over the second electrically insulating layer; and

removing portions of one or more of the first metal layer, the second electrically insulating layer, and the second metal layer.

2. The method of claim 1 wherein:

the first electrically insulating layer comprises a first electrically insulating material; and

conformally depositing the first metal layer comprises conformally depositing a layer comprising a first metal having a work function that lies approximately mid-way between a conductive band and a valence band of the first electrically insulating material.

3. The method of claim 2 wherein:

conformally depositing the second metal layer comprises conformally depositing a layer comprising the first metal.

4. The method of claim 3 wherein:

conformally depositing the second electrically insulating layer comprises conformally depositing a high-k dielectric material.

5. The method of claim 1 wherein:

removing portions of one or more of the first metal layer, the second electrically insulating layer, and the second metal layer comprises creating an upper extremity of the second electrically insulating layer; and

the method further comprises recessing the second metal layer below the upper extremity of the second electrically insulating layer.

6. The method of claim 1 further comprising:

adjusting a height of the first semiconducting fin.

7. The method of claim 6 wherein:

a surface of the first electrically insulating layer is a first surface;

the first semiconducting fin has a second surface and the second electrically conducting layer has a third surface;

a width of the trench is a first distance;

a distance between the first surface and the second surface is a second distance and a distance between the second surface and the third surface is a third distance; and

adjusting the height of the first semiconducting fin comprises causing the height of the first semiconducting fin to be between approximately six times and approximately twelve times greater than the first distance.

8. The method of claim 1 wherein the first semiconducting fin is at least partially enclosed by an electrically conducting material and the method further comprises:

removing a portion of the inter-layer dielectric in order to expose a surface of the electrically conducting material; and

removing the electrically conducting material in order to form the trench.

9. The method of claim 8 wherein:

removing the electrically conducting material comprises:

depositing an electrically insulating film over the inter-layer dielectric surface;

defining an opening for the tri-gate capacitor, thereby exposing a portion of the electrically insulating film; and

removing the portion of the electrically insulating film.

10. The method of claim 9 wherein:

removing the electrically conducting material further comprises etching the electrically conducting material using a wet etch.

11. A system comprising:

a board;

a processing device disposed on the board; and

a dynamic random access memory cell disposed on and coupled to the processing device,

wherein:

the dynamic random access memory cell comprises a tri-gate storage capacitor and a tri-gate transistor to the tri-gate storage capacitor, the tri-gate storage capacitor comprising:

a substrate;

a first electrically insulating layer over the substrate;

a silicon fin over the first electrically insulating layer;

a first electrically conducting layer over the first electrically insulating layer and adjacent to the silicon fin;

a second electrically insulating layer adjacent to the first electrically conducting layer; and

a second electrically conducting layer adjacent to the second electrically insulating layer;

the first electrically insulating layer comprises an oxide layer having a first surface; and

the fin is a silicon fin having a first portion extending into the first electrically insulating layer and having a second portion protruding from the first surface.

12. The system of claim 11 wherein:

the second electrically insulating layer comprises a high-k dielectric material.