Programmable metallization cell with alloy layer

1. A programmable metallization cell (PMC) memory comprising:

a top electrode and a bottom electrode;

a metal layer between the top and bottom electrodes; and

a solid electrolyte (SE) layer between the metal layer and the bottom electrode;

wherein the metal layer includes an alloy of at least first and second metals;

wherein the first metal includes at least one of copper, silver, nickel, or combinations thereof, and the second metal includes at least one of palladium, platinum, tungsten, cobalt, or combinations thereof.

2. The memory of claim 1 comprising a barrier layer between the metal layer and the top electrode.

3. The memory of claim 2 , wherein the metal layer directly contacts the SE layer.

4. The memory of claim 3 , wherein metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased.

5. A system comprising:

a processor;

a memory, coupled to the processor, according to claim 1 ; and

a communication module, coupled to the processor, to communicate with a computing node external to the system.

6. A memory comprising:

a top electrode and a bottom electrode;

a metal layer between the top and bottom electrodes; and

a solid electrolyte (SE) layer between the metal layer and the bottom electrode;

wherein the metal layer includes an alloy of at least one metal and at least one of copper, silver, nickel, or combinations thereof;

wherein the metal layer comprises less than 50% of the at least one of copper, silver, nickel, or combinations thereof.

7. The memory of claim 6 comprising a barrier layer between the metal layer and the top electrode.

8. The memory of claim 7 , wherein the metal layer directly contacts the SE layer.

9. The memory of claim 7 , wherein:

at least ⅓ of the at least one of copper, silver, nickel, or combinations thereof is included in an upper third of the metal layer, the upper third of the metal layer being adjacent the barrier layer; and

the barrier layer includes at least one of Ta, Ti, W, or combinations thereof.

10. The memory of claim 6 , wherein the metal layer is at least 3 nm thick.

11. The memory of claim 6 , wherein:

a bottom ⅕ th of the metal layer includes a first percentage of the at least one of copper, silver, nickel, or combinations thereof;

at least one of an upper 1/10 th , upper ⅖ th , upper ⅗ th , upper ⅘ th , or upper ⅕ th of the metal layer includes a second percentage of the at least one of copper, silver, nickel, or combinations thereof;

the second percentage is greater than the first percentage.

12. The memory of claim 11 , wherein the at least one metal includes at least one of Palladium, Platinum, Tungsten, Cobalt, Aluminum, or combinations thereof.

13. The memory of claim 11 , wherein the memory is a programmable metallization cell (PMC).

14. The memory of claim 13 , wherein the lower electrode is a cathode and the metal layer is an anode when the top electrode is biased positively.

15. The memory of claim 6 , wherein metal ions from the metal layer form a conductive path in the SE layer when the top electrode is biased with a first polarity and disband the conductive path when the top electrode is biased with a second polarity that is opposite the first polarity.

16. The memory of claim 15 , wherein the metal ions are oxidized ions of the at least one of copper, silver, nickel, or combinations thereof.

17. The memory of claim 6 , wherein the SE layer includes at least one of silver-doped germanium selenide, silver-doped germanium sulfide, copper-doped germanium sulfide, Al 2 O 3 , HfO 2 , SiO 2 , ZrO 2 , TiO 2 , or combinations thereof.

18. The memory of claim 17 , wherein the bottom electrode includes at least one TiN, TaN, W, Ru, or combinations thereof and the top electrode includes at least one of W, Cu, Al, or combinations thereof.

19. A method comprising:

forming a bottom electrode;

forming a solid electrolyte (SE) layer on the bottom electrode;

forming a metal layer directly contacting an upper surface of the SE layer, the metal layer including an alloy of at least first and second metals;

forming a barrier layer on the metal layer;

forming a top electrode on the barrier layer;

patterning the SE layer, the metal layer, and the barrier layer to form a programmable metallization cell (PMC) memory; and

controlling a percentage of the first metal in the alloy to be less than 50% of the alloy.

20. The method of claim 19 , wherein the first metal includes at least one of copper, silver, nickel, or combinations thereof and the second metal includes at least one of palladium, platinum, tungsten, cobalt, aluminum, or combinations thereof.

21. The method of claim 20 comprising controlling a thickness of the metal layer to be at least 5 nm.

22. The method of claim 19 , wherein metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased.