Vertical nanowire transistor with axially engineered semiconductor and gate metallization
View Patent ↗Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
1. A vertical nanowire transistor, comprising:
a source region vertically aligned with a drain region along a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the source region comprising a first semiconductor material and the drain region comprising a second semiconductor material different from the first semiconductor material;
a channel region disposed between the source and drain region along the longitudinal axis, the channel region comprising a third semiconductor material different from the first and second semiconductor materials, wherein the first semiconductor material comprises germanium, and the third semiconductor material comprises silicon germanium; and
an annular gate electrode surrounding a side all of the channel region, separated by an annular gate dielectric layer, wherein a work function of the gate electrode is greater proximate to the drain region than proximate to the source region.
2. The vertical nanowire transistor of claim 1 , wherein the first semiconductor material is germanium and the second semiconductor material is silicon germanium.
3. The vertical nanowire transistor of claim 1 , wherein the first semiconductor material is silicon germanium, and wherein a total atomic concentration of germanium is greater in the first semiconductor material than in the third semiconductor material.
4. The vertical nanowire transistor of claim 1 , wherein the channel region has a compositional variation between a first interface with the source region and a second interface with the drain region.
5. The vertical nanowire transistor of claim 4 , wherein the compositional variation comprises a grading of the third semiconductor layer.
6. The vertical nanowire transistor of claim 5 , wherein the third semiconductor material is a Site alloy, and wherein the Ge content is higher at the first interface than at the second interface.
7. The vertical nanowire transistor of claim 1 , wherein a gate electrode composition of the gate electrode is graded from a first alloy composition proximate to the source region to a second alloy composition proximate to the drain region.
8. The vertical nanowire transistor of claim 1 , wherein the channel region comprises a lightly doped or intrinsic high mobility injection layer disposed proximate to the source region.
9. A method of fabricating a vertical nanowire transistor, the method comprising:
epitaxially growing a source region above a crystalline substrate, the source region comprising a first semiconductor material;
epitaxially growing a channel region on the source region, the channel region comprising a second semiconductor material different from the first semiconductor material;
epitaxially growing a drain region on the channel region, the drain region comprising a third semiconductor material different from the first and second semiconductor materials, wherein the drain region and the channel region are vertically aligned with the source region along a longitudinal axis perpendicularly oriented to a surface plane of the crystalline substrate, wherein the first semiconductor material comprises germanium, and the third semiconductor material comprises silicon germanium; and
forming an annular gate electrode surrounding a sidewall of the channel region, separated by an annular gate dielectric layer, wherein a work function of the gate electrode is greater proximate to the drain region than proximate to the source region.
10. The method of claim 9 , wherein the first semiconductor material is germanium and the third semiconductor material is silicon germanium.
11. The method of claim 9 , wherein the first semiconductor material is silicon germanium, and wherein a total atomic concentration of germanium is greater in the first semiconductor material than in the third semiconductor material.
12. The method of claim 9 , wherein the channel region has a compositional variation between a first interface with the source region and a second interface with the drain region.
13. The method of claim 12 , wherein the compositional variation comprises a grading of the third semiconductor layer.
14. The method of claim 13 , wherein the third semiconductor material is a SiGe alloy, and wherein the Ge content is higher at the first interface than at the second interface.
15. The method of claim 9 , wherein a gate electrode composition of the gate electrode is graded from a first alloy composition proximate to the source region to a second alloy composition proximate to the drain region.
16. The method of claim 9 , wherein epitaxially growing the channel region comprises forming a lightly doped or intrinsic high mobility injection layer disposed proximate to the source region.
17. A vertical nanowire transistor, comprising:
a source region vertically aligned with a drain region along a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the source region comprising a first semiconductor material and the drain region comprising a second semiconductor material different from the first semiconductor material;
a channel region disposed between the source and drain region along the longitudinal axis, the channel region comprising a third semiconductor material different from the first and second semiconductor materials; and
an annular gate electrode surrounding a sidewall of the channel region, separated by an annular gate dielectric layer, wherein a work function of the gate electrode is greater proximate to the drain region than proximate to the source region.
18. The vertical nanowire transistor of claim 17 , wherein a gate electrode composition of the gate electrode is graded from a first alloy composition proximate to the source region to a second alloy composition proximate to the drain region.
19. The vertical nanowire transistor of claim 17 , wherein the channel region comprises a lightly doped or intrinsic high mobility injection layer disposed proximate to the source region.
20. A method of fabricating a vertical nanowire transistor, the method comprising:
epitaxially growing a source region above a crystalline substrate, the source region comprising a first semiconductor material;
epitaxially growing a channel region on the source region, the channel region comprising a second semiconductor material different from the first semiconductor material;
epitaxially growing a drain region on the channel region, the drain region comprising a third semiconductor material different from the first and second semiconductor materials, wherein the drain region and the channel region are vertically aligned with the source region along a longitudinal axis perpendicularly oriented to a surface plane of the crystalline substrate; and
forming an annular gate electrode surrounding a sidewall of the channel region, separated by an annular gate dielectric layer, wherein a work function of the gate electrode is greater proximate to the drain region than proximate to the source region.
21. The method of claim 20 , wherein a gate electrode composition of the gate electrode is graded from a first alloy composition proximate to the source region to a second alloy composition proximate to the drain region.
22. The method of claim 20 , wherein epitaxially growing the channel region comprises forming a lightly doped or intrinsic high mobility injection layer disposed proximate to the source region.