Method for fabricating transistor with thinned channel
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
1. An apparatus comprising:
a first portion of a semiconductor body, wherein the first portion is under a gate electrode, and wherein the first portion has a first width, wherein the gate electrode is a tri-gate structure; and
a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width, and wherein the semiconductor body is a fin on a substrate; and
a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, and
wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV, and wherein the gate electrode is of an n-type device.
2. The apparatus of claim 1 , wherein the second portion is closer to drain or source regions.
3. The apparatus of claim 2 , wherein the source and drain regions comprise As or Ph.
4. The apparatus of claim 1 , wherein the gate electrode includes a work function metal comprising: W, Ta, Ti, and N.
5. The apparatus of claim 1 , wherein the substrate comprises Si.
6. The apparatus of claim 5 , wherein the substrate comprises a delta-doped substrate.
7. The apparatus of claim 1 , wherein the gate electrode is between a first spacer and a second spacer, and wherein the first and second spacers comprise N.
8. The apparatus of claim 1 , wherein the gate dielectric comprises Hf and O.
9. The apparatus of claim 1 , wherein the first structure comprises Si and O, and wherein the second structure comprises Hf and O.
10. The apparatus of claim 1 , wherein the gate electrode has a work function in a range of 4.6 eV to 5.2 eV, and wherein the gate electrode is of a p-type device.
11. A system comprising:
a memory;
a processor; and
a network interface coupled to the processor via a bus, wherein the processor is at least one of: a central processing unit (CPU); a graphics processor; a digital signal processor; or a crypto processor, wherein the memory comprises at least one of a volatile memory or non-volatile memory, and wherein the processor includes:
a first portion of a semiconductor body, wherein the first portion is under a gate electrode, wherein the first portion has a first width, and wherein the gate electrode is a tri-gate structure; and
a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width, and wherein the semiconductor body is a fin on a substrate; and
a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV, and wherein the gate electrode is of an n-type device.
12. The system of claim 11 , wherein the second portion is closer to drain or source regions.
13. The system of claim 12 , wherein the source and drain regions comprise As or Ph.
14. The system of claim 11 , wherein the gate electrode includes a work function metal comprising: W, Ta, Ti, and N.
15. The system of claim 11 , wherein the substrate comprises Si.
16. The system of claim 11 , wherein the gate electrode is between a first spacer and a second spacer, and wherein the first and second spacers comprises N.
17. The system of claim 11 , wherein the gate dielectric comprises Hf and O.
18. The system of claim 11 , wherein the first structure comprises Si and O, and wherein the second structure comprises Hf and O.
19. A method comprising:
forming a first portion of a semiconductor body, wherein the first portion is under a gate electrode, wherein the first portion has a first width, and wherein the gate electrode is a tri-gate structure; and
forming a second portion of the semiconductor body outside the gate electrode, wherein the second portion has a second width, wherein the second width is greater than the first width, and wherein the semiconductor body is a fin on a substrate; and
forming a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric is a dual layer gate dielectric having a first structure and a second structure, wherein the gate electrode has a work function in a range of 3.9 eV to 4.6 eV, and wherein the gate electrode is of an n-type device.
20. The method of claim 19 , wherein the second portion is closer to drain or source regions.