IP Library Granted Patent US 10,943,792
Granted Patent B2
US 10,943,792 · App. 16/325,665 · Granted Mar 9, 2021

3D stacked-in-recess system in package

Inventors: Bok Eng Cheah (Bukit Gambir, MY); Min Suet Lim (Simpang Ampat, MY); Jackson Chung Peng Kong (Tanjung Tokong, MY); Howe Yin Loo (Sungai Petani, MY)
Assignee: Intel Corporation
H01L21/48H01L23/00H01L23/48H01L23/538H01L23/552H01L25/0652H01L25/0655H01L25/18H01L25/50H01L29/0657H01L2224/13025H01L2224/16146H01L2224/16225H01L2224/16235H01L2224/17181H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/1432H01L2924/1434H01L2924/15192H01L2924/15311H01L2924/3025
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Quick Facts
Patent No.
US 10,943,792
App. No.
16/325,665
Granted
Mar 9, 2021
Kind
B2
Abstract

A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.

Claims (43)

1. A system in package device comprising:

a landed first die disposed on a package substrate, wherein the landed first die includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein the backside surface includes a first contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge;

a stacked first die disposed in the contoured recess and on the ledge, wherein the landed first die and the stacked first die are each contacted by a first through-silicon via (TSV);

a landed subsequent die disposed on the package substrate, wherein the landed subsequent die includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein the die backside surface includes a subsequent contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge; and

wherein the landed subsequent die and the stacked first die are each contacted by a subsequent TSV;

wherein the stacked first die is configured as a communication bridge between the landed first die and the landed subsequent die.

2. The system in package device of claim 1 ,

wherein the stacked first die is configured as a communication bridge between the landed first die and the landed subsequent die.

3. The system in package device of claim 2 , wherein the landed first- and subsequent dice have different die heights that are measured from the respective active- and backside surfaces.

4. The system in package device of claim 2 , wherein the first contoured recess and subsequent contoured recess form a composite contoured recess formed by respective notches formed in the landed first- and subsequent dice.

5. The system in package device of claim 2 , wherein the first contoured recess and subsequent contoured recess form a composite contoured recess formed by respective notches formed in the landed first- and subsequent dice, and wherein the landed first die includes an input/output (I/O) core region through which the landed first die communicates to the stacked first die through the first TSV.

6. The system in package device of claim 2 , wherein the first contoured recess and subsequent contoured recess form a composite contoured recess formed by respective notches formed in the landed first- and subsequent dice, further including a stacked subsequent die also disposed in the composite contoured recess.

7. The system in package device of claim 6 , further including a second-tier first die stacked upon the stacked first- and subsequent dice.

8. The system in package device of claim 7 , wherein the second-tier first die is a shielded baseband processor, and wherein at least one of the landed first- and second dice is a central processing unit.

9. A system in package device comprising:

a landed first die disposed on a package substrate, wherein the landed first die includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein the backside surface includes a first contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge;

a stacked first die disposed in the contoured recess and on the ledge, wherein the landed first die and the stacked first die are each contacted by a first through-silicon via (TSV);

a landed subsequent die disposed on the package substrate, wherein the landed subsequent die includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein the die backside surface includes a subsequent contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge; and

wherein the landed subsequent die and the stacked first die are each contacted by a subsequent TSV;

wherein the stacked first die is configured as a communication bridge between the landed first die and the landed subsequent die;

wherein the stacked first die is configured as a communication bridge between the landed first die and the landed subsequent die: and

a landed third die and a stacked subsequent die, and wherein the landed third die includes a first- and second notch, wherein the first notch forms a composite contoured recess with the first die notch and the stacked first die is in the composite contoured recess between the landed first- and third dice, and wherein the second notch forms a composite contoured recess with the subsequent die notch, and wherein the stacked subsequent die is in the composite contoured recess between the landed third- and subsequent dice.

10. The system in package device of claim 9 , wherein at least two of the landed first- subsequent- and third dice have different die heights that are measured from the respective active- and backside surfaces.

11. A system in package device comprising:

at least three landed dice disposed on a package substrate, each landed die of which includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein each die backside surface includes a contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge;

a stacked first die disposed on at least one ledge of the at least three landed dice, wherein the at least one landed die and the stacked first die are each contacted by a first through-silicon via (TSV); and

wherein two of the at least three landed dice include a landed first die and a landed second die.

12. The system in package of claim 11 , wherein one of the at least three landed dice includes a landed subsequent die disposed on the package substrate, wherein the landed subsequent die and the stacked first die are each contacted by a subsequent TSV;

wherein the stacked first die is configured as a communication bridge between the landed first die and the landed subsequent die; and

wherein the landed first die, landed second die, and landed subsequent die are configured substantially linearly.

13. The system in package of claim 11 , wherein the three landed dice occupy a right-angle configuration.

14. The system in package of claim 11 , further including a fourth landed die, wherein the four landed dice are configured in a T shape.

15. The system in package of claim 11 , further including fourth- and a fifth landed dice, where the five landed dice are configured in a cross shape.

16. A system in package computing system comprising:

a landed first die disposed on a package substrate, wherein the landed first die includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein the backside surface includes a first contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge;

a stacked first die disposed in the contoured recess and on the ledge, wherein the landed first die and the stacked first die are each contacted by a first through-silicon via (TSV):

a landed subsequent die disposed on the package substrate, wherein the landed subsequent die includes an active surface, a die backside surface, a lateral first edge and a lateral second edge, and wherein the die backside surface includes a subsequent contoured recess that opens the die backside surface to a ledge at one of the lateral first edge and lateral second edge;

wherein the landed subsequent die and the stacked first die are each contacted by a subsequent TSV; and

wherein the stacked first die is configured as a communication bridge between the landed first die and the landed subsequent die;

a component disposed on the package substrate; and

wherein the system in package device is part of a chipset that uses a processor and a memory.

17. The computing system of claim 16 , wherein the landed first die is disposed on the package substrate on a die side, and wherein the package substrate includes is bumped in a bump array on a land side that is opposite the die side.

18. The computing system of claim 16 , wherein the landed first die is disposed on the package substrate on a die side, and wherein the package substrate includes a land side that is opposite the die side, and wherein the land side is part of an external shell for the computing system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
Continuity (1)
Related Publication 20190206698A1 · Jul 4, 2019