Current-mode digital temperature sensor apparatus
View Patent ↗Described is a current-mode thermal sensor apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second transistor with a gate terminal coupled to a second node; a first resistor coupled to the first and second nodes; a second resistor coupled to the first node and a supply node; and a diode coupled to the second node and the supply node.
1. An apparatus comprising:
a first transistor with a gate terminal coupled to a first node;
a second transistor with a gate terminal coupled to a second node;
a first resistor coupled to the first and second nodes;
a second resistor coupled to the first node and a supply node; and
a diode having a first terminal coupled to the gate terminal of the second transistor via the second node, the diode having a second terminal coupled to the supply node.
2. The apparatus of claim 1 , wherein the first and second transistors are configured to operate in weak inversion mode.
3. The apparatus of claim 1 , wherein the first and second transistors are configured to form a differential pair.
4. The apparatus of claim 1 , wherein the first and second transistors are configured to provide a PTAT signal.
5. The apparatus of claim 1 , wherein the diode is configured to provide a CTAT signal on the first and second nodes.
6. The apparatus of claim 1 , wherein the supply node is a ground node.
7. The apparatus of claim 1 further comprises a current source coupled to a common node of the first and second transistors.
8. The apparatus of claim 1 further comprises a current mirror to provide:
a first current through the first transistor, and
a second current through the second transistor.
9. The apparatus of claim 8 , wherein the current mirror is configured to cause the second current to be a multiple of the first current.
10. The apparatus of claim 8 further comprises:
an amplifier including inputs coupled to nodes of the current mirror, and an output; and
a buffer including an input coupled to the output of the amplifier, and an output coupled to the first node.
11. The apparatus of claim 10 , wherein the buffer comprises devices that coupled together provide a non-linear characteristic.
12. The apparatus of claim 1 further comprises a current source to provide a third current through a third transistor, wherein the third transistor is coupled to the second node.
13. The apparatus of claim 1 further comprises a circuit to adjust resistance of the second resistor.
14. The apparatus of claim 13 , wherein the circuit comprises a digital-to-analog converter (DAC).
15. The apparatus of claim 1 , wherein the diode is one of:
a device which produces a voltage drop with negative temperature coefficient;
Schottky-contact diode;
a discrete diode;
a lateral bipolar diode;
a diode formed from a MOS transistor; or
a BJT based diode.
16. The apparatus of claim 1 , wherein the first and second resistors are coupled together in series.
17. An apparatus comprising:
a first transistor with a gate terminal coupled to a first node;
a second transistor with a gate terminal coupled to a second node;
a first resistor coupled to the first and second nodes;
a second resistor coupled to the first node and a ground node;
a third transistor coupled in series with the first and second resistors;
a current mirror to provide a first current through the first transistor, a second current through the second transistor, and a third current through a third transistor; and
a diode having a first terminal coupled to the gate terminal of the second transistor via the second node, the diode having a second terminal coupled to the ground node, the diode to receive a part of the third current.
18. The apparatus of claim 17 , wherein the first and second transistors are configured to operate in weak inversion mode.
19. The apparatus of claim 17 further comprises a circuit to adjust resistance of the second resistor.
20. The apparatus of claim 17 , wherein the first and second transistors are configured to provide a PTAT signal.
21. The apparatus of claim 17 , wherein the diode is configured to provide a CTAT signal on the first and second nodes.
22. A system comprising:
a memory unit;
a processor coupled to the memory unit, the processor having a temperature sensor which includes:
a first transistor with a gate terminal coupled to a first node;
a second transistor with a gate terminal coupled to a second node;
a first resistor coupled to the first and second nodes;
a second resistor coupled to the first node and a supply node; and
a diode having a first terminal coupled to the gate terminal of the second transistor via the second node, the diode having a second terminal coupled to the supply node; and
a wireless interface for allowing the processor to communicate with another device.
23. The system of claim 22 further comprises a display unit for displaying content processed by the processor.