Forming barrier walls, capping, or alloys /compounds within metal lines
View Patent ↗Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.
1. A structure comprising:
a metal interconnect formed in a trenched layer of dielectric material of the structure, wherein the metal interconnect further includes:
a vertical interconnect access (VIA) that is formed at each end of the metal interconnect;
a barrier layer formed at least along upper surfaces of the vertical interconnect access (VIA) and the metal interconnect, wherein a conductive layer is deposited as gap fill in the barrier layer;
a barrier wall formed on and above the barrier layer and within the metal interconnect, wherein the barrier wall is filled with a treated conductive layer to form a diffusion barrier.
2. The structure of claim 1 , wherein the barrier wall is deposited within patterned backend structures orthogonal to a direction of the metal interconnect forming a wall within the metal interconnect that stops the flow of metal conductor ions.
3. The structure of claim 1 , wherein the barrier wall is present every 1 to 2 micrometers (μm) along the metal interconnect.
4. The structure of claim 1 , wherein the barrier wall deposited in an etch selective Cu recess forming an isotropic Cu.
5. The structure of claim 1 , wherein the barrier wall is one of Tantalum (Ta), Ruthenium (Ru), Ru alloy, or materials with diffusion barrier properties, or combination thereof.
6. The structure of claim 1 , wherein the barrier wall has thickness from 0.1 to 10 nanometers (nm).
7. The structure of claim 1 , wherein the barrier layer is one of Titanium Nitride (TiN), Tantalum Nitride (TaN), Tungsten Nitride (WN), Tantalum Nitride (TaN), Tungsten Nitride (WN), Ruthenium (Ru), Ruthenium alloy, other materials with diffusion barrier properties, or a combination thereof.
8. The structure of claim 1 wherein the conductive layer is Copper (Cu).
9. The structure of claim 1 wherein a chemical mechanical polishing (CMP) process is performed to remove or polish excess conductive layer and the barrier layer on the surface of the layer of dielectric material.
10. A metal interconnect comprising:
a trenched layer of dielectric material that includes a vertical interconnect access (VIA) that is formed at each end of the trenched layer;
a barrier layer formed at least along upper surfaces of the vertical interconnect access (VIA) and the trenched layer, wherein a conductive layer is deposited as gap fill in the barrier layer; and
a barrier wall formed on and above the barrier layer, wherein the barrier wall is filled with a treated conductive layer to form a diffusion barrier.
11. The metal interconnect of claim 10 , wherein the barrier wall is deposited within patterned backend structures orthogonal to a direction of the metal interconnect forming a wall within the metal interconnect that stops the flow of metal conductor ions.
12. The metal interconnect of claim 10 , wherein the barrier wall is not formed near the VIAs.
13. The metal interconnect of claim 10 , wherein the barrier wall is present every 1 to 2 micrometers (μm) along the metal interconnect.