Integrating non-peripheral component interconnect (PCI) resources into a personal computer system

1. An apparatus comprising:

an adapter adapted on a single semiconductor die to communicate with a first component according to a personal computer (PC) protocol and to communicate with a first interface according to a second protocol corresponding to an advanced extensible interface (AXI) or open core protocol (OCP) protocol;

the first interface adapted on the single semiconductor die and coupled to the adapter by a first interconnect, the first interface to perform address translation and ordering of transactions received from the first component; and

a second interconnect adapted on the single semiconductor die to couple the first interface to a plurality of heterogeneous resources adapted on the single semiconductor die, each of the plurality of heterogeneous resources including an intellectual property (IP) core and a shim, wherein the shim is to implement a peripheral component interconnect (PCI) header for the IP core to enable incorporation of the corresponding IP core in the apparatus without modification, wherein the apparatus is to operate according to the PC protocol and the IP core is to operate according to the second protocol.

2. The apparatus of claim 1 , wherein the first interface is to translate configuration cycles of the PC protocol into a format for the second protocol, wherein the PC protocol corresponds to the peripheral component interconnect (PCI) protocol.

3. The apparatus of claim 2 , wherein the first interface is to perform the address translation to translate a re-locatable PCI address into an AXI/OCP address.

4. The apparatus of claim 1 , wherein the first interface is to perform operations that are common across the plurality of heterogeneous resources, and each shim is to perform operations that are specific to the corresponding IP core.

5. The apparatus of claim 4 , wherein the common operations include the address translation and the ordering, and the specific operations include power management and error handling.

6. The apparatus of claim 5 , wherein the ordering is to satisfy a producer-consumer model of the PC protocol.

7. The apparatus of claim 1 , wherein the second interconnect comprises an auto-generated interconnect fabric.

8. The apparatus of claim 2 , wherein the first interface is to route accesses to the PCI header to a corresponding shim, and the shim is to implement the PCI header for the corresponding IP core, wherein the first interface is to further route accesses to a device memory space to the corresponding shim.

9. The apparatus of claim 8 , wherein the corresponding shim is to consume all read-write operations to the PCI header and is to communicate other transactions to the corresponding IP core.

10. A system comprising:

a processor;

a host interface coupled to the processor, the host interface to couple the processor to a memory and an adapter;

the adapter coupled to the host interface to communicate according to a personal computer (PC) protocol and to communicate with a second interface according to a second protocol corresponding to an advanced extensible interface (AXI) or open core protocol (OCP) protocol;

the second interface coupled to the adapter by a first interconnect, the second interface to perform address translation and ordering of transactions received from the processor; and

a second interconnect to couple the second interface to a plurality of heterogeneous resources, each of the plurality of heterogeneous resources including an intellectual property (IP) core and a shim, wherein the shim is to implement a peripheral component interconnect (PCI) header for the IP core to enable incorporation of the corresponding IP core in the system without modification, wherein the system is to operate according to the PC protocol and the IP core is to operate according to the second protocol.

11. The system of claim 10 , wherein the system comprises an ultra mobile system, wherein the processor is to execute a PC operating system using the PC protocol.

12. The system of claim 11 , wherein the second interface is to translate configuration cycles of the PC protocol into a format for the second protocol, wherein the PC protocol corresponds to a peripheral component interconnect (PCI) protocol and the second interface is to perform the address translation to translate a re-locatable PCI address into an AXI/OCP address.

13. The system of claim 12 , wherein the second interface is to perform operations that are common across the plurality of heterogeneous resources, and each shim is to perform operations that are specific to the corresponding IP core, the common operations including the address translation and the ordering, and the specific operations including low power management and error handling.

14. The system of claim 12 , wherein the second interface is to route accesses to the PCI header to a corresponding shim, and the shim is to implement the PCI header for the corresponding IP core, wherein the second interface is to further route accesses to a device memory space to the corresponding shim and wherein the corresponding shim is to consume all read-write operations to the PCI header and is to communicate other transactions to the corresponding IP core.

15. An apparatus comprising:

an adapter adapted on a single semiconductor die to communicate with a first component according to a peripheral component interconnect (PCI) protocol and to communicate with a first interface according to a second protocol corresponding to an advanced extensible interface (AXI) protocol;

the first interface adapted on the single semiconductor die and coupled to the adapter by a first interconnect, the first interface to perform address translation and ordering of transactions received from the first component, wherein the first interface is to translate configuration cycles of the PCI protocol into a format for the second protocol; and

a second interconnect adapted on the single semiconductor die to couple the first interface to a plurality of heterogeneous resources adapted on the single semiconductor die, each of the plurality of heterogeneous resources including an intellectual property (IP) core and a shim, wherein the shim is to implement a PCI header for the IP core to enable incorporation of the corresponding IP core in the apparatus without modification, wherein the apparatus is to operate according to the PCI protocol and the IP core is to operate according to the second protocol.

16. The apparatus of claim 15 , wherein the first interface is to perform the address translation to translate a re-locatable PCI address into an AXI address.

17. The apparatus of claim 15 , wherein the first interface is to perform operations that are common across the plurality of heterogeneous resources, and each shim is to perform operations that are specific to the corresponding IP core.

18. The apparatus of claim 17 , wherein the common operations include the address translation and the ordering, and the specific operations include power management and error handling.

19. The apparatus of claim 15 , wherein the corresponding shim is to consume all read-write operations to the PCI header and is to communicate other transactions to the corresponding IP core.