Strained channel region transistors employing source and drain stressors and systems including the same
View Patent ↗Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.
1. A device comprising:
a substrate having a source region and a drain region, wherein the source region and the drain region comprise a III-V compound semiconductor material, and the III-V compound semiconductor material comprises one or more elements from group III of the periodic table and one or more elements from group V of the periodic table;
a channel region, wherein the channel region is comprised of a plurality of nanowires or nanoribbons, the channel region is between the source and the drain region, a first end of the plurality of nanowires or nanoribbons abuts the source region, a second end of the plurality of nanowires or nanoribbons abuts the drain region;
a gate dielectric material around the plurality of nanoribbons or nanowires; and
a gate electrode material on the gate dielectric.
2. The device of claim 1 , wherein the channel region comprises germanium.
3. The device of claim 2 , wherein the channel region further comprises silicon.
4. The device of claim 1 , wherein the one or more elements from group III of the periodic table are selected from the group consisting of B, Al, Ga, and In, and the one or more elements from group V of the periodic table are selected from the group consisting of P, As, and Sb.
5. The device of claim 1 , wherein the source region and the drain region comprise Al x In 1-x P with 0.5<x<0.8, Ga x In 1-x P with 0.5<x<0.8, GaSb x P 1-x with 0.1<x<0.3, AlSb x P 1-x with 0.1<x<0.3, AlAs x P 1-x with 0.5<x<1, or GaAs x P 1-x with 0.5<x<1.
6. The device of claim 1 wherein the source region and the drain region comprise Al x In 1-x P with x between 0.2 and 0.5, Ga x In 1-x P with x between 0.2 and 0.5, Ga x In 1-x As with x between 0.7 and 1, Al x In 1-x P with x between 0.7 and 1, GaSb x P 1-x with x between 0.3 and 0.5, AlSb x P 1-x with x between 0.3 and 0.5, GaAs x Sb 1-x with x between 0.75 and 1, or AlAs x Sb 1-x with x between 0.75 and 1.
7. The device of claim 1 , wherein the channel region is tensely strained.
8. The device of claim 1 , wherein the channel region is compressively strained.
9. The device of claim 1 , wherein the source and drain regions are doped with germanium, carbon, silicon, magnesium, beryllium, manganese, or zinc.
10. The device of claim 1 , further comprising insulating spacers that abut the gate electrode material.
11. A computing device comprising:
a motherboard;
a communication chip mounted on the motherboard; and
a processor mounted on the motherboard, the processor comprising a transistor, the transistor comprising:
a substrate having a source region and a drain region, wherein the source and the drain regions comprise a III-V compound semiconductor material, and the III-V compound semiconductor material comprises one or more elements from group III of the periodic table and one or more elements from group V of the periodic table,
a channel region, wherein the channel region is comprised of a plurality of nanowires or nanoribbons, the channel region is between the source and the drain regions, a first end of the plurality of nanowires or nanoribbons abuts the source region and a second end of the plurality of nanowires or nanoribbons abuts the drain region,
a gate dielectric material around the plurality of nanoribbons or nanowires, and
a gate electrode material on the gate dielectric.
12. The computing device of claim 11 , wherein the one or more elements from group III of the periodic table are selected from the group consisting of B, Al, Ga, and In, and the one or more elements from group V of the periodic table are selected from the group consisting of P, As, and Sb.
13. The computing device of claim 11 , wherein the source and the drain region comprise Al x In 1-x P with 0.5<x<0.8, Ga x In 1-x P with 0.5<x<0.8, GaSb x P 1-x with 0.1<x<0.3, AlSb x P 1-x with 0.1<x<0.3, AlAs x P 1-x with 0.5<x<1, GaAs x P 1-x with 0.5<x<1, Al x In 1-x P with x between 0.2 and 0.5, Ga x In 1-x P with x between 0.2 and 0.5, Ga x In 1-x As with x between 0.7 and 1, Al x In 1-x P with x between 0.7 and 1, GaSb x P 1-x with x between 0.3 and 0.5, AlSb x P 1-x with x between 0.3 and 0.5, GaAs x Sb 1-x with x between 0.75 and 1, or AlAs x Sb 1-x with x between 0.75 and 1.
14. The computing device of claim 11 , wherein the plurality of nanowires or nanoribbons comprises four nanowires or nanoribbons.
15. The computing device of claim 11 , wherein the III-V compound semiconductor material has a lattice mismatch with a material of the plurality of nanowires or nanoribbons.