Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects

1. A back end of line (BEOL) metallization layer for a semiconductor structure, the BEOL metallization layer comprising:

an inter-layer dielectric (ILD) layer disposed above a substrate;

a plurality of conductive lines disposed in the ILD layer along a first direction; and

a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and

a conductive via coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

2. The BEOL metallization layer of claim 1 , further comprising:

a dielectric plug disposed adjacent the conductive via and breaking continuity of one of the plurality of conductive lines, the dielectric plug having an uppermost surface planar with the uppermost surface of the via hardmask.

3. The BEOL metallization layer of claim 2 , wherein the dielectric plug is composed of a material different than the ILD layer.

4. The BEOL metallization layer of claim 2 , wherein the dielectric plug is composed of a same material as the ILD layer and is continuous with the ILD layer.

5. The BEOL metallization layer of claim 1 , wherein the conductive tab is continuous with the two of the plurality of conductive lines.

6. The BEOL metallization layer of claim 1 , wherein the plurality of conductive lines has a pitch of 20 nanometers or less.

7. The BEOL metallization layer of claim 1 , wherein each of the plurality of conductive lines has a width of 10 nanometers or less.

8. A back end of line (BEOL) metallization layer for a semiconductor structure, the BEOL metallization layer comprising:

an inter-layer dielectric (ILD) layer disposed above a substrate;

a plurality of conductive lines disposed in the ILD layer along a first direction; and

a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and

a dielectric plug breaking continuity of one of the plurality of conductive lines, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the dielectric plug is planar with one another, and wherein the dielectric plug is composed of a material different than the ILD layer.

9. The BEOL metallization layer of claim 8 , wherein the conductive tab is continuous with the two of the plurality of conductive lines.

10. The BEOL metallization layer of claim 8 , wherein the plurality of conductive lines has a pitch of 20 nanometers or less.

11. The BEOL metallization layer of claim 8 , wherein each of the plurality of conductive lines has a width of 10 nanometers or less.

12. A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, the integrated circuit comprising a back end of line (BEOL) metallization layer for a semiconductor structure, the BEOL metallization layer comprising:

an inter-layer dielectric (ILD) layer disposed above a substrate;

a plurality of conductive lines disposed in the ILD layer along a first direction; and

a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and

a conductive via coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

13. The computing device of claim 12 , further comprising:

a memory coupled to the board.

14. The computing device of claim 12 , further comprising:

a communication chip coupled to the board.

15. The computing device of claim 12 , further comprising:

a camera coupled to the board.

16. The computing device of claim 12 , further comprising:

a battery coupled to the board.

17. The computing device of claim 12 , wherein the component is a packaged integrated circuit die.

18. A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, the integrated circuit comprising a back end of line (BEOL) metallization layer for a semiconductor structure, the BEOL metallization layer comprising:

an inter-layer dielectric (ILD) layer disposed above a substrate;

a plurality of conductive lines disposed in the ILD layer along a first direction; and

a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and

a dielectric plug breaking continuity of one of the plurality of conductive lines, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the dielectric plug is planar with one another, and wherein the dielectric plug is composed of a material different than the ILD layer.

19. The computing device of claim 18 , further comprising:

a memory coupled to the board.

20. The computing device of claim 18 , further comprising:

a communication chip coupled to the board.

21. The computing device of claim 18 , further comprising:

a camera coupled to the board.

22. The computing device of claim 18 , further comprising:

a battery coupled to the board.

23. The computing device of claim 18 , wherein the component is a packaged integrated circuit die.