Memory channel that supports near memory and far memory access
View Patent ↗A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
1. A semiconductor chip comprising:
system memory controller circuitry having interface circuitry to couple to a system memory channel, the system memory controller circuitry including:
first logic circuitry to implement a first system memory channel protocol on the memory channel through the interface circuitry, said first system memory channel protocol specific to a first volatile system memory technology;
second logic circuitry to implement a second system memory channel protocol on the system memory channel through the interface circuitry, said second system memory channel protocol specific to a second non volatile system memory technology, said second system memory channel protocol being a transactional protocol.
2. The semiconductor chip of claim 1 wherein said first volatile system memory technology is DRAM and said second non volatile system memory technology comprises a phase change material.
3. The semiconductor chip of claim 1 wherein said system memory channel includes a command bus, a data bus and control lines.
4. The semiconductor chip of claim 1 wherein said first logic circuitry is designed to not receive a read request from said first interface as part of implementing said first system memory channel protocol and wherein said second logic circuitry is designed to a read request from said interface as part of implementing said second system memory channel protocol.
5. A computer system, comprising:
system memory controller circuitry having interface circuitry to couple to a system memory channel, the system memory controller circuitry including:
first logic circuitry to implement a first system memory channel protocol on the system memory channel through the interface circuitry, said first system memory channel protocol specific to a first volatile system memory technology;
second logic circuitry to implement a second system memory channel protocol on the system memory channel through the interface circuitry, said second system memory channel protocol specific to a second non volatile system memory technology, said second system memory channel protocol being a transactional protocol;
a first system memory device composed of the first volatile system memory technology coupled to the system memory channel; and,
a second system memory device composed of the second non volatile system memory technology coupled to the system memory channel.
6. The computer system of claim 5 wherein said first type of system memory technology is DRAM and said second type of system memory technology comprises a phase change material.
7. The computer system of claim 5 wherein said system memory channel includes a command bus, a data bus and control lines.
8. The computer system of claim 7 further comprising, along said command bus, far memory control logic circuitry between the channel and the second system memory device.
9. The computer system of 8 wherein said far memory control circuitry is also between said channel and said first system memory device along said command bus.