Power reduction for system on chip
View Patent ↗Disclosed herein are SOC devices with peripheral units having power management logic.
1. A system-on-a-chip integrated circuit, comprising:
a processor core;
a peripheral unit communicatively coupled to the processor core, the peripheral unit comprising power management logic to determine when the peripheral unit may go into a power reduction state and to request entry into the power reduction state; and
a clock provided to the peripheral unit, the clock comprising clock control logic coupled between the processor core and the peripheral unit to provide the clock to the peripheral unit, wherein the clock control logic comprises a power mode status bit for the peripheral unit to indicate if the peripheral unit is in the power reduction state, wherein the power management logic comprises a separate power mode status bit that mirrors the power mode status bit in the clock control logic, and wherein the processor core causes the clock to be reduced in servicing the power reduction request through control of the power mode status bit.
2. The integrated circuit of claim 1 , comprising an interrupt controller to receive the power reduction request and provide the power reduction request to the processor core to service the power reduction request.
3. The integrated circuit of claim 2 , in which the peripheral unit is coupled to the processor core via an internal bus.
4. The integrated circuit of claim 1 , in which the power mode status bits in the clock control logic and the power management logic are hard coupled to one another.
5. A method, comprising:
within an SOC, receiving a power reduction request from a peripheral unit generated by power management logic within the peripheral unit; and
sending a signal to cause power consumption in the peripheral unit to be reduced in response to the power reduction request, wherein power consumption is to be reduced by reducing a clock provided to the peripheral unit, the clock comprising clock control logic to provide the clock to the peripheral unit, wherein the clock control logic comprises a power mode status bit for the peripheral unit to indicate if the peripheral unit is in the power reduction state, wherein the power management logic comprises a separate power mode status bit that mirrors the power mode status bit in the clock control logic, and wherein the clock is reduced through control of the power mode status bit.
6. The method of claim 5 , wherein receiving the power reduction request comprises receiving an interrupt service request from the peripheral unit through an interrupt controller.
7. The method of claim 6 , comprising determining that the peripheral unit is ready for power reduction before sending the signal to cause power consumption to be reduced.
8. The method of claim 7 , wherein determining that the peripheral unit is ready for power reduction comprises checking a ready bit within the power management logic.
9. A wireless communications device, comprising:
an SOC comprising a processor core, a peripheral unit communicatively coupled to the processor core, the peripheral unit having power management logic to determine when the peripheral unit may go into a power reduction state and to request entry into the power reduction state, and a clock provided to the peripheral, the clock comprising clock control logic coupled between the processor core and the peripheral unit to provide the clock to the peripheral unit, wherein the clock control logic comprises a power mode status bit for the peripheral unit to indicate if the peripheral unit is in the power reduction state, wherein the power management logic comprises a separate power mode status bit that mirrors the power mode status bit in the clock control logic, and wherein the processor core causes the clock to be reduced in servicing the power reduction request through control of the power mode status bit;
an antenna coupled to the processor core through a wireless interface; and
a serial communications interface coupled to the processor core through the peripheral unit.
10. The device of claim 9 , in which the SOC further comprises an interrupt controller to receive the power reduction request and provide the power reduction request to the processor core to service the power reduction request.
11. The device of claim 10 , in which the peripheral unit is coupled to the processor core via an internal bus.
12. The device of claim 9 , in which the peripheral unit comprises a USB controller.