Gate-induced strain for MOS performance improvement

1. An apparatus comprising:

a substrate;

a device over the substrate including a gate electrode over a surface of the substrate; and

a straining material disposed over the gate electrode, the straining material having at least one of a lattice spacing that is different than a lattice spacing of the gate electrode, a coefficient of linear thermal expansion of the straining material that is different than a coefficient of linear thermal expansion of a material of the gate electrode, and an intrinsic stress in the straining material.

2. The apparatus of claim 1 , wherein the gate electrode is under a strain caused by at least one of the different lattice spacing of the straining material; a thermal expansion mismatch of the straining material and a material of the gate electrode; and an intrinsic strain in the straining material.

3. The apparatus of claim 1 , wherein the gate electrode comprises a material having a first lattice spacing that comprises a different lattice spacing than a second lattice spacing of the straining material.

4. The apparatus of claim 1 , wherein the gate electrode is under a compressive strain caused by the straining material having a first lattice spacing being a smaller lattice spacing than a second lattice spacing of the gate electrode.

5. The apparatus of claim 1 , wherein the gate electrode is under a tensile strain caused by the straining material having a first lattice spacing being a larger lattice spacing than a second lattice spacing of the gate electrode material.

6. The apparatus of claim 1 , wherein the substrate further comprise a channel region.

7. The apparatus of claim 6 , wherein the channel region is under a strain caused by at least one of a different lattice spacing of the straining material;

a thermal expansion mismatch of the straining material and a material of the gate electrode; and

an intrinsic strain in the straining material.

8. The apparatus of claim 7 , wherein the channel region is under a tensile strain.

9. The apparatus of claim 7 , wherein the channel region is under a compressive strain.

10. The apparatus of claim 1 , wherein the substrate further comprises a channel region, and wherein the channel region comprises a material having a first lattice spacing that comprises a different lattice spacing than a second lattice spacing of the straining material.

11. The apparatus of claim 1 , wherein the substrate further comprises a channel region, and wherein the channel region is under a compressive strain caused by a first lattice spacing of the straining material being a smaller lattice spacing than a second lattice spacing of the channel region.

12. The apparatus of claim 1 , wherein the straining material comprises an epitaxial layer of a silicon alloy material.

13. The apparatus of claim 1 , wherein the straining material comprises a material selected from the group consisting of silicon (Si), silicon germanium (Si y-x Ge x ), silicon carbide (Si y-x C x ), nickel silicide (NiSi), titanium silicide (TiSi 2 ), and cobalt silicide (CoSi 2 ).

14. The apparatus of claim 1 , wherein the straining material comprises silicon doped with at least one of boron, carbon, nitrogen, and phosphorous.

15. The apparatus of claim 1 , wherein the straining material comprises silicon doped with at least one of aluminum, galium, germanium, arsenic, indium, tin, and antimony.

16. An apparatus comprising:

a substrate;

a device over the substrate including a gate electrode over a top surface of the substrate, and a first junction region and a second junction region in the substrate adjacent the gate electrode; and

a straining material having at least one of a lattice spacing that is different than a lattice spacing of the gate electrode, a coefficient of linear thermal expansion of the straining material that is different than a coefficient of linear thermal expansion of a material of the gate electrode, and an intrinsic stress, in the straining material, the straining material disposed over the gate electrode.

17. The apparatus of claim 16 , wherein the straining material comprises silicon germanium having a lattice spacing that is larger than a lattice spacing of the substrate adapted to impart a tensile strain in the gate electrode.

18. An apparatus comprising:

a substrate defining an interior of the apparatus;

a device exterior to the substrate comprising a gate electrode; and

a straining layer exterior to the device and exterior to the substrate, the straining material having at least one of a lattice spacing that is different than a lattice spacing of the gate electrode, a coefficient of linear thermal expansion of the straining material that is different than a coefficient of linear thermal expansion of a material of the gate electrode, and an intrinsic stress in the straining material, the straining layer disposed over the gate electrode.

19. The apparatus of claim 18 , further comprising a gate dielectric exterior to the substrate, interior to the gate electrode, and interior to the straining layer.

20. The apparatus of claim 19 , wherein the gate dielectric comprises at least one of an aluminum nitride, an aluminum oxide, a silicon nitride, and a silicon oxide.

21. The apparatus of claim 19 , wherein the substrate further comprises a channel, wherein the channel is interior to the gate dielectric, interior to the gate electrode, and interior to the straining layer.

22. The apparatus of claim 18 , wherein the substrate further comprises a channel.

23. The apparatus of claim 22 , wherein the channel is interior to the gate electrode, and interior to the straining layer.

24. The apparatus of claim 23 , wherein the substrate further comprises at least two junction regions adjacent the channel.

25. An apparatus comprising:

a substrate; and

a device over the substrate including a gate electrode over a top surface of the substrate, and a first junction region and a second junction region in the substrate adjacent the gate electrode; and

a straining material having a lattice spacing that is different than a lattice spacing of the gate electrode, the straining material disposed over the gate electrode.