Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations

1. A memory comprising:

a memory array;

a resistor coupled to a reference voltage;

on die termination circuitry coupled with the resistor; and

an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a first calibration command to calibrate the on die termination circuitry, the first calibration command having an associated first calibration time window, and a second calibration command to calibrate the on die termination circuitry, the second calibration command having an associated second calibration time window, wherein the first calibration time window is greater than the second calibration time window, and further wherein the memory array is quiesced responsive, at least in part, to the first calibration command.

2. The memory of claim 1 , wherein the memory array is a Dynamic Random Access Memory.

3. The memory of claim 1 , wherein the first calibration command is a ZQ calibration command and the resistor is a ZQ pin.

4. The memory of claim 1 , wherein the first calibration command is sent during initialization of the memory.

5. The memory of claim 1 , wherein the second calibration command is sent after the memory is initialized.

6. A method comprising:

receiving a first command to calibrate on die termination circuitry in a memory, the first command having an associated first calibration time window;

placing a memory input and an output and a memory core in a quiet mode;

using a resistor connected to a reference voltage to calibrate the on die termination circuitry to compensate for at least one of a process, a voltage and a temperature variation; and

receiving a second command to calibrate on die termination circuitry in the memory, the second command having an associated second calibration time window, wherein the first calibration time window is greater than the second calibration time window.

7. The method of claim 6 , wherein receiving a first command to calibrate on die termination circuitry in a memory is a command to calibrate a Dynamic Random Access Memory.

8. The method of claim 6 , wherein using a resistor connected to a reference voltage to calibrate the on die termination circuitry uses a ZQ pin on the memory.

9. The method of claim 6 , comprising sending the first calibration command during initialization of the memory.

10. The method of claim 6 , comprising sending the second calibration command after the memory is initialized.

11. A system comprising:

a processor;

a display device in electrical communication with the processor;

a memory controller coupled with the processor; and

a memory coupled with the memory controller, the memory comprising:

a memory array;

a resistor coupled to a reference voltage;

on die termination circuitry coupled with the resistor; and

an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a first calibration command to calibrate the on die termination circuitry, the first calibration command having an associated first calibration time window, and a second calibration command to calibrate the on die termination circuitry, the second calibration command having an associated second calibration time window, wherein the first calibration time window is greater than the second calibration time window, and further wherein the memory array is quiesced responsive, at least in part, to the first calibration command.

12. The system of claim 11 , comprising drive circuitry coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and to calibrate the drive circuitry with the resistor coupled to the reference voltage.

13. The system of claim 11 , wherein the memory array is a Dynamic Random Access Memory.

14. The system of claim 11 , wherein the first calibration command is a ZQ calibration command and the resistor is a ZQ pin.