Method and apparatus for efficient store/restore of state information during a power state
A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.
1. A processor comprising:
a plurality of power domains including a first power domain for a first processor component and a second power domain for a second processor component; and
streamlining circuitry to:
obtain from a memory, for a power state transition from a first power state to a second power state, respective addresses for:
internal state information of each power domain that is disabled in the first power state, and
internal state information of each power domain that is to be disabled in the second power state, and
compare the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information stored.
2. The processor of claim 1 wherein said streamlining circuitry is to cause a store of the internal state information for each of the plurality of power domains determined.
3. The processor of claim 1 wherein said streamlining circuitry is to obtain meta data for each of the plurality of power domains determined to have their internal state information stored.
4. The processor of claim 3 wherein said meta data describes a sequence at which certain items of internal state information are to be accessed.
5. The processor of claim 3 wherein said meta data describes a time delay before a certain item of internal state information is to be accessed.
6. The processor of claim 1 wherein said second power domain includes the first processor component and the second processor component.
7. The processor of claim 1 wherein the first processor component is a first core and the second processor component is a second core.
8. The processor of claim 1 wherein the first processor component is a first core and the second processor component is a cache separate from the first core.
9. The processor of claim 1 , wherein the streamlining circuitry is to further compare the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information restored.
10. A method comprising:
providing a plurality of power domains of a processor including a first power domain for a first processor component and a second power domain for a second processor component;
obtaining, with streamlining circuitry for a power state transition from a first power state to a second power state, respective addresses for:
internal state information of each power domain that is disabled in the first power state, and
internal state information of each power domain that is to be disabled in the second power state, and
comparing the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information stored.
11. The method of claim 10 further comprising storing the internal state information for each of the plurality of power domains that are determined.
12. The method of claim 10 further comprising obtaining meta data for each of the plurality of power domains determined to have their internal state information stored.
13. The method of claim 12 wherein said meta data describes a sequence at which certain items of internal state information are to be accessed and said method further comprises said streamlining circuitry accessing said items of internal state information in said sequence.
14. The method of claim 12 wherein said meta data describes a time delay before a certain item of internal state information is to be accessed and said method further comprises said streamlining circuitry imposing said time delay before accessing said certain item of internal state information.
15. The method of claim 10 wherein said second power domain includes the first processor component and the second processor component.
16. The method of claim 10 , further comprising comparing the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information restored.
17. A computing system comprising:
a plurality of power domains including a first power domain for a first processor component and a second power domain for a second processor component;
a memory to store for each of a plurality of power states:
i) respective addresses for internal state information of a power domain of a power state,
ii) respective addresses of a memory where said internal state information is to be stored when said power domain is powered down, and
iii) meta data for transferring said internal state information between said power domain and where said internal state information is to be stored when said power domain is powered down; and
streamlining circuitry coupled to said memory to:
obtain from the memory, for a power state transition from a first power state to a second power state, respective addresses for:
internal state information of each power domain that is disabled in the first power state, and
internal state information of each power domain that is to be disabled in the second power state, and
compare the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information stored.
18. The computing system of claim 17 wherein said streamlining circuitry is to cause a store of the internal state information for each of the plurality of power domains that are determined.
19. The computing system of claim 17 wherein said streamlining circuitry is to obtain meta data for each of the plurality of power domains determined to have their internal state information stored.
20. The computing system of claim 17 wherein said meta data describes a sequence at which certain items of said internal state information are to be accessed.
21. The computing system of claim 17 wherein said meta data describes a time delay before a certain item of said internal state information is to be accessed.
22. The computing system of claim 17 wherein said streamlining circuitry provides said memory with an identity of a power state to which said power domain pertains before receiving i), ii), and iii) above.
23. The computing system of claim 17 , wherein the streamlining circuitry is to further compare the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information restored.