Fast exit from self-refresh state of a memory device
View Patent ↗A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition.
1. A method comprising:
changing from a self-refresh state to a standard refresh state of a memory device, where the self-refresh state disables a clock within the memory device in response to a command by an associated memory controller to temporarily suspend access operations of the memory device; and
triggering a self-refresh state indicator of the memory device responsive to changing from the self-refresh state to the standard refresh state to indicate to the associated memory controller that the memory device has exited from the self-refresh state and the memory controller can resume sending access commands to the memory device.
2. The method of claim 1 , wherein changing from the self-refresh state to the standard refresh state comprises:
changing states in response to a self-refresh timer.
3. The method of claim 1 , wherein triggering the self-refresh state indicator comprises:
setting a pin of the memory device.
4. The method of claim 1 , wherein triggering the self-refresh state indicator comprises:
generating a self-refresh state change indicator on a clock enable (CKE) channel.
5. An apparatus comprising:
memory resources to store data;
an input control line to receive a clock signal; and
memory resource control logic coupled to the memory resources, the memory resource control logic to
change from a self-refresh state to a standard refresh state, where the self-refresh state disables the clock within the memory resources in response to a command by an associated memory controller to temporarily suspend access operations of the memory resources; and
switch a self-refresh state indicator responsive to changing from the self-refresh state to the standard refresh state to indicate to the associated memory controller that the memory resources have exited from the self-refresh state and the memory controller can resume sending access commands to the memory resources.
6. The apparatus of claim 5 , wherein the memory resources comprise memory resources of a memory bank within a memory device.
7. The apparatus of claim 5 , wherein the memory resource control logic is to switch the self-refresh state indicator by setting a pin of the apparatus to a logic state corresponding to the standard refresh state.
8. The apparatus of claim 5 , wherein the memory resource control logic is to switch the self-refresh indicator by toggling a logic state of a pin of the apparatus.
9. A method comprising:
checking a self-refresh state indicator for a dynamic random access memory (DRAM);
determining with a memory controller whether to access the DRAM by determining whether the self-refresh state indicator indicates the DRAM is in self-refresh or whether the self-refresh state indicator indicates the DRAM has exited self-refresh and the memory controller can resume sending access commands to the DRAM, where self-refresh disables a clock within the memory device to temporarily suspend access operations of the DRAM;
if the DRAM is in self-refresh, selecting a self-refresh wait time; otherwise,
selecting a guard band wait time;
where the self-refresh wait time indicates an amount of time a memory controller should wait before checking the self-refresh indicator again and is an amount of time less than a refresh cycle time for the DRAM, and the guard band wait time indicates a minimum time between commands sent to the DRAM from the memory controller; and
sending a command at the end of the guard band wait time.
10. The method of claim 9 , wherein the self-refresh wait time comprises a refresh cycle time (tRFC) for the DRAM.
11. The method of claim 9 , wherein determining whether the self-refresh state indicator indicates the DRAM is in self-refresh further comprises:
the memory controller receiving a self-refresh indicator signal from the DRAM.
12. The method of claim 9 , wherein selecting the self-refresh wait time further comprises:
selecting a wait time, where the wait time indicates how long to wait between making polling attempts to determine whether to access the DRAM.
13. The method of claim 9 , wherein selecting the self-refresh wait time further comprises:
waiting until a self-refresh exit interrupt is received from the DRAM.
14. A system comprising:
a memory device having
multiple memory resources to store data;
an input control line to receive a clock signal; and
memory resource control logic coupled to the memory resources, the control logic to change from a self-refresh state to a standard refresh state, where the self-refresh state disables the clock within the memory resources in response to a command by an associated memory controller to temporarily suspend access operations of the memory resources, and switch a self-refresh state indicator responsive to changing from the self-refresh state to the standard refresh state to indicate to the associated memory controller that the memory resources have exited from the self-refresh state and the memory controller can resume sending access commands to the memory resources; and
a memory controller to manage access to data stored on the memory device, the memory controller to
determine whether to access the memory device by determining whether the self-refresh state indicator indicates the memory device is in a self-refresh state;
if the memory device is in the self-refresh state, select a self-refresh wait time;
otherwise, select a guard band wait time; where the self-refresh wait time indicates an amount of time a memory controller should wait before determining again whether the self-refresh state indicator indicates the memory device is in a self-refresh state, and the guard band wait time indicates a minimum time between commands sent to the memory device from a memory controller; and
send a command at the end of the guard band wait time.
15. The system of claim 14 , wherein the control logic is to switch the self-refresh state indicator by setting a pin of the apparatus to a logic state corresponding to the standard refresh state.
16. The system of claim 15 , wherein the pin comprises a bidirectional clock enable (CKE) channel, wherein the memory device drives the channel to indicate exit from self-refresh, and wherein otherwise the memory controller drives the channel.
17. The system of claim 14 , wherein the memory controller is to select the self-refresh wait time by selecting a wait time, where the wait time indicates how long to wait between making polling attempts of the self-refresh state indicator to determine whether to access the memory device.