Memory with dynamically adjustable supply
View Patent ↗In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
1. A circuit, comprising:
an array comprising: a plurality of memory cells disposed in columns and rows, each column having cells coupled to a common supply line and a virtual supply driver coupled between the supply line and a supply reference to controllably provide to its column of cells at least one of a normal and a collapsed supply level, the virtual supply driver to be controlled to provide the collapsed supply level when a cell in its column is to be written, the collapsed supply level to be provided for a sufficiently small time to avoid losing states in cells of the column not to be written.
2. The circuit of claim 1 , in which the array comprises a wordline in each row to controllably activate cells in a row when a cell in the row is to be written, the virtual supply driver in each column to be controlled to return from the collapsed supply level to the normal supply level before an activated wordline is de-activated.
3. The circuit of claim 1 , in which the supply line is a VCC line, and the supply reference is a VCC supply voltage.
4. The circuit of claim 1 , in which the supply line is a VSS line, and the supply reference is a VSS reference.
5. The circuit of claim 1 , in which the collapsed supply level, when provided at the supply line of a column, causes the voltages supplied across the cells in the column to be less than ⅓ of a normal VCC supplied to the cells for at least part of the time that the supply line is at the collapsed level.
6. The circuit of claim 5 , in which the collapsed supply level, when provided at the supply line of a column, causes the voltages supplied across the cells in the column to substantially approach 0V.
7. A circuit, comprising:
an array comprising: a plurality of memory cells disposed in columns and rows each row having cells coupled to a common supply line and a virtual supply driver coupled between the supply line and a supply reference to controllably provide to the cells in its row at least one of a normal and a collapsed supply level, the array to perform a write operation by reading the row containing a cell to be written, writing back to the row the read cells except writing into the cell to be written a desired value, the virtual supply driver to be controlled to provide the collapsed supply level to the cells in its row when cells in its row when they are written to during the write operation.
8. The circuit of claim 7 , in which the supply line is a VCC line, and the supply reference is a VCC supply voltage.
9. The circuit of claim 7 , in which the supply line is a VSS line, and the supply reference is a VSS reference.
10. The circuit of claim 7 , in which the collapsed supply level, when provided at the supply line of a row, causes the voltages supplied across the cells in the row to be less than ⅓ of a normal VCC supplied to the cells for at least part of the time that the supply line is at the collapsed level.
11. The circuit of claim 10 , in which the collapsed supply level, when provided at the supply line of a row, causes the voltages supplied across the cells in the row to substantially approach 0V.
12. The circuit of claim 7 , comprising at least one separate sense amplifier coupled to each column so that the cells of a row may all be read pursuant to the write operation.