Integrated circuit package substrate
View Patent ↗Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
1. A package substrate comprising:
a first side;
a second side opposite the first side;
one or more lands on the first side;
one or more die bond pads on the second side, wherein the one or more die bond pads are located in a die interconnect region, wherein the die interconnect region comprises a silicon bridge;
a first surface finish on at least one of the lands; and
a second surface finish on at least one of the die bond pads;
wherein the second surface finish has a different chemical composition than the first surface finish.
2. The package substrate of claim 1 , wherein at least one die bond pad is on the silicon bridge.
3. The package substrate of claim 1 , wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more die bond pads.
4. The package substrate of claim 1 , wherein the second surface finish is imidazole or an imidazole derivative.
5. The package substrate of claim 1 , wherein the second surface finish is gold (Au).
6. The package substrate of claim 1 , wherein the second surface finish is a combination of palladium (Pd) and gold (Au).
7. The package substrate of claim 1 , wherein the second surface finish has a thickness of less than or equal to 500 nanometers.
8. The package substrate of claim 1 , wherein the first surface finish comprises nickel (Ni).
9. The package substrate of claim 8 , wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).
10. An assembly comprising:
a first die;
a second die;
a silicon bridge disposed on a substrate;
a plurality of lands disposed on a first side of the substrate;
a plurality of die bond pads, at least one die bond pad disposed on the silicon bridge and
at least one other die bond pad disposed on a second side of the substrate, the second side of the substrate opposite the first side;
a first surface finish on at least one of the lands; and
a second surface finish on at least one of the die bond pads, wherein the second surface finish has a different chemical composition than the first surface finish;
a first set of interconnect structures extending between the first die and the die bond pads; and
a second set of interconnect structures extending between the second die and the die bond pads.
11. The assembly of claim 10 , further comprising routing features disposed in the silicon bridge electrically coupling the first die and the second die.
12. The assembly of claim 11 , further comprising routing features disposed in the substrate electrically coupling the first die and the second die.
13. The assembly of claim 10 , wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more die bond pads.
14. The assembly of claim 10 , wherein the second surface finish is imidazole or an imidazole derivative.
15. The assembly of claim 10 , wherein the second surface finish is gold (Au).
16. The assembly of claim 10 , wherein the second surface finish is a combination of palladium (Pd) and gold (Au).
17. The assembly of claim 10 , wherein the second surface finish has a thickness of less than or equal to 500 nanometers.
18. The assembly of claim 10 , wherein the first surface finish comprises nickel (Ni).
19. The assembly of claim 18 , wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).