Sleep transistor array apparatus and method with leakage control circuitry

1. A chip, comprising:

a plurality of sleep transistors to provide a virtual supply during an active mode;

a memory to enable a predetermined combination of said sleep transistors during the active mode based on active mode leakage; and

a controller to program the memory at startup to enable the predetermined combination during the active mode.

2. The chip of claim 1 , in which the memory comprises a scan register.

3. The chip of claim 2 , in which the memory further comprises a plurality of one time programmable cells.

4. The chip of claim 1 , in which the virtual supply is a virtual high supply reference, and the sleep transistors comprise PMOS transistors.

5. The chip of claim 4 , in which the predetermined combination is determined based on active leakage measurements of a die associated with the chip.

6. The chip of claim 1 , in which the virtual supply is provided to a portion of the chip.

7. A method comprising:

measuring a chip's active mode leakage;

if necessary, reducing the conductance of a sleep transistor array to identify a combination of enabled sleep transistors resulting in satisfactory leakage; and

programming the chip so that the identified combination of sleep transistors is enabled during active modes when the chip is in operation, wherein measuring comprises initially enabling each transistor in the array.

8. The method of claim 7 , in which programming comprises burning an array of one time programmable memory cells to store the identified combination.

9. The method of claim 7 , in which programming comprises storing the identified combination in firmware to be executed by a controller in the chip.

10. The method of claim 7 , further comprising confirming that the chip is sufficiently fast.