IP Library Granted Patent US 10,249,588
Granted Patent B2
US 10,249,588 · App. 15/369,815 · Granted Apr 2, 2019

Designs and methods for conductive bumps

Inventors: Valery M. Dubin (Portland, OR); Sridhar Balakrishnan (Portland, OR); Mark Bohr (Aloha, OR)
Assignee: Intel Corporation
H01L24/13H01L21/288H01L21/4853H01L24/05H01L24/11H01L2224/0401H01L2224/05124H01L2224/1145H01L2224/11452H01L2224/11462H01L2224/11464H01L2224/11614H01L2224/1312H01L2224/13026H01L2224/13084H01L2224/13099H01L2224/13111H01L2224/13113H01L2224/13139H01L2224/13147H01L2224/13166H01L2224/13564H01L2224/13611H01L2224/13639H01L2224/13647H01L2224/29111H01L2924/014H01L2924/01005H01L2924/01006H01L2924/01013H01L2924/01015H01L2924/01022H01L2924/01023H01L2924/01024H01L2924/01027H01L2924/01029H01L2924/01033H01L2924/01042H01L2924/01044H01L2924/01045H01L2924/01047H01L2924/01051H01L2924/01057H01L2924/01058H01L2924/01074H01L2924/01076H01L2924/01077H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/01327H01L2924/04941H01L2924/14H01L2924/3011H01L2924/351H01L2924/35121H01L2924/3651
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Quick Facts
Patent No.
US 10,249,588
App. No.
15/369,815
Granted
Apr 2, 2019
Kind
B2
Abstract

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Claims (31)

1. A method of forming an assembly, comprising:

providing a substrate, the substrate having a metal pad including aluminum, a base layer metal (BLM) disposed on the metal pad, the BLM including titanium, a bump disposed on the BLM, the bump including copper, and a first solder layer disposed on the bump, the first solder layer including tin and having a first material composition;

providing a die package, the die package having a first side and an opposing second side, and a second solder layer disposed on the first side of the die package, the second solder layer including tin and having a second material composition different from the first material composition, wherein one of the first solder layer or the second solder layer comprises an element not included in the other of the first solder layer or the second solder layer;

connecting the second solder layer of the die package to the first solder layer of the substrate to enable electrical current to flow between the die package and the substrate.

2. The method of claim 1 , wherein the bump is disposed directly on the BLM.

3. The method of claim 1 , wherein the base layer metal (BLM) further includes copper.

4. The method of claim 1 , wherein the first solder layer further includes silver.

5. The method of claim 1 , wherein the second solder layer on the die package further includes silver and copper.

6. The method of claim 1 , wherein the substrate further comprises a diffusion barrier layer disposed between the bump and the first solder layer.

7. The method of claim 6 , wherein the substrate further comprises a wetting layer disposed between the diffusion barrier layer and the first solder layer.

8. The method of claim 6 , wherein the diffusion barrier layer includes phosphorous.

9. The method of claim 1 , wherein the assembly is substantially free of lead.

10. The method of claim 1 , wherein one of the first solder layer and the second solder layer comprises an element not included in the other of the first solder layer and the second solder layer.

11. A method of forming an assembly, comprising:

forming a metal pad on a substrate, the metal pad including aluminum;

forming a base layer metal (BLM) on the metal pad, the BLM including titanium;

forming a bump on the BLM, the bump including copper;

forming a first solder layer on the bump, the first solder layer including tin and having a first material composition;

forming a second solder layer on a side of a die package, the second solder layer including tin and having a second material composition different from the first material composition, wherein one of the first solder layer or the second solder layer comprises an element not included in the other of the first solder layer or the second solder layer; and

subsequent to forming the metal pad, the BLM, the bump, the first solder layer and the second solder layer, connecting the second solder layer of the die package to the first solder layer of the substrate to enable electrical current to flow between the die package and the substrate.

12. The method of claim 11 , wherein the bump is formed directly on the BLM.

13. The method of claim 11 , wherein the base layer metal (BLM) further includes copper.

14. The method of claim 11 , wherein the first solder layer further includes silver.

15. The method of claim 11 , wherein the second solder layer formed on the die package further includes silver and copper.

16. The method of claim 11 , further comprising:

forming a diffusion barrier layer on the bump, wherein the first solder layer is formed on the diffusion barrier layer.

17. The method of claim 16 , further comprising:

forming a wetting layer on the diffusion barrier layer, wherein the first solder layer is formed on the wetting layer.

18. The method of claim 16 , wherein the diffusion barrier layer includes phosphorous.

19. The method of claim 11 , wherein the assembly is substantially free of lead.

20. The method of claim 11 , wherein one of the first solder layer and the second solder layer comprises an element not included in the other of the first solder layer and the second solder layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
Continuity (4)
Continuation 12973615 · Dec 20, 2010
Continuation 11894627 · Aug 20, 2007
Division 10668986 · Sep 22, 2003
Related Publication 20170084564A1 · Mar 23, 2017