Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same
Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
1. A semiconductor package substrate, comprising:
a first build-up film including a first lithograph surface;
a second and adjacent build-up film including a recess that abuts the first lithographic surface; and
a magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess.
2. The semiconductor package substrate of claim 1 , further including a complementary magnetic-particle body that contacts the inductor trace, the first magnetic-particle body and the first build-up film.
3. The semiconductor package substrate of claim 1 , further including:
a thin-film capacitor, wherein the thin-film capacitor is seated on the first lithographic surface, and at least partially embedded in the second and adjacent build-up film, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side; and
a first capacitor via that communicates to the die side and that contacts the thin-film capacitor.
4. The semiconductor package substrate of claim 1 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:
a package via that communicates from the die side, through the first build-up film, the second and adjacent build-up film, and that further communicates to the land side.
5. The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side further including:
a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the integral magnetic inductor, wherein the semiconductive device forms a die shadow on the die side, and wherein the die shadow overlaps the integral magnetic inductor.
6. The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side further including:
a ball-pad array on the die side, where ball-pad pad array is exposed through a die-side solder resist semiconductive device contacting the die side, wherein the ball-pad array is coupled to the integral magnetic inductor, wherein the ball-pad array forms a die shadow on the die side, and wherein the die shadow overlaps the integral magnetic inductor.
7. The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, and the magnetic inductor is a first magnetic inductor, further including:
a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent the first magnetic inductor, wherein the subsequent magnetic inductor includes a subsequent inductor trace and a subsequent first magnetic-particle body within the recess, and a subsequent complementary magnetic-particle body that contacts the subsequent inductor trace, the subsequent first magnetic-particle body and the first build-up film.
8. The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, wherein the recess is a first recess, and wherein the magnetic inductor is a first magnetic inductor, further including:
a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent the first magnetic inductor, wherein the subsequent magnetic inductor includes two subsequent inductor traces and a subsequent first magnetic-particle body within a subsequent recess with the second and adjacent build-up film, and a subsequent complementary magnetic-particle body that contacts the two subsequent inductor traces, the subsequent first magnetic-particle body and the first build-up film.
9. The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:
a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the integral magnetic inductor;
an electrical bump on the land side; and
a board contacting the electrical bump.
10. The semiconductor package substrate of claim 3 , further including a subsequent capacitor via that communicates to the die side and that contacts the thin-film capacitor.
11. The semiconductor package substrate of claim 3 , wherein the thin-film capacitor includes, beginning at first lithographic surface, a copper-containing layer, a nickel-containing layer, a barium titanate (BTO) containing layer and a copper-containing layer.
12. The semiconductor package substrate of claim 3 , wherein the thin-film capacitor includes, beginning at first lithographic surface, a first metal-containing layer, a subsequent metal-containing layer different from the first metal-containing layer, a dielectric layer and a third metal-containing layer.
13. A process of forming a semiconductor package substrate, comprising:
locating an inductor trace and a first magnetic-particle paste in a recess in an adjacent build up film;
locating a subsequent complementary magnetic-particle paste adjacent the first magnetic particle paste, wherein the subsequent complementary magnetic-particle paste contacts the inductor trace, and wherein the first and subsequent complementary magnetic-particle paste and the inductor trace are part of a magnetic inductor;
forming a land side and a die side that are coupled to the first and second and adjacent build-up films; and
wherein the die side includes a die footprint that overlaps the magnetic inductor.
14. The process of claim 13 , wherein the inductor trace is a first inductor trace, further including locating a subsequent inductor trace with the first magnetic-particle paste in the recess in the adjacent build up film;
locating the subsequent complementary magnetic-particle paste adjacent the first magnetic particle paste, wherein the subsequent complementary magnetic-particle paste contacts the first inductor trace and the subsequent inductor trace.
15. A computing system, comprising:
a first build-up film of a semiconductor package substrate, wherein the first build-up film includes a first lithograph surface, and wherein the semiconductor package substrate includes a die side and a land side;
a second and adjacent build-up film including a recess that abuts the first lithographic surface;
an integral magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess;
a semiconductive device contacting the die side, wherein the semiconductive device is coupled to integral magnetic inductor, wherein the semiconductive device forms a die shadow on the die side, and wherein the die shadow overlaps the integral magnetic inductor; and
a board contacting the semiconductor package substrate at the land side.
16. The computing system of claim 15 , further including a complementary magnetic-particle body that contacts the inductor trace, the first magnetic-particle body and the first build-up film.
17. The computing system of claim 15 , further wherein the semiconductive device is part of a chipset.
18. The computing system of claim 15 , further wherein the semiconductive device is part of a chipset, wherein the hoard includes an external shell, further including:
a thin-film capacitor, wherein the thin-film capacitor is seated on the first lithographic surface, and at least partially embedded in the second and adjacent build-up film.
19. The computing system of claim 16 , wherein the board is part of a data server.
20. The computing system of claim 16 , wherein the board includes an external shell.
21. The computing system of claim 18 , and wherein the embedded thin-film capacitor is one of more than three embedded thin-film capacitors.