High-voltage transistor architectures, processes of forming same, and systems containing same

1. A process of forming a transistor, comprising:

forming a gate upon a semiconductive substrate above a channel;

forming an interlayer dielectric layer (ILD0) above and on the semiconductive substrate;

opening a source via in the ILD0 to expose a source implant in the channel;

opening a drain via in the ILD0 to expose a drain implant in a drain well in the semiconductive substrate, wherein the drain well forms a junction with the channel;

saliciding a source contact pad in the source implant, and a drain contact pad in the drain implant; and

filling the respective source and drain vias with source and drain contacts at the respective contact pads.

2. The process of claim 1 , wherein the gate is a high-K metal gate, wherein the channel is a P-well, wherein the drain well is an N-well, wherein the high-K metal gate has a first lateral dimension between the first side and the second side, wherein the N drain well has a second lateral dimension, and wherein the second lateral dimension is equal to or greater than the first lateral dimension.

3. The process of claim 2 , wherein the transistor is a first device in a first region of the semiconductive substrate, the process further including:

forming a subsequent device in a region separate from the first device, wherein the first device is configured to operate at a voltage higher than the subsequent device; and

forming at least seven metallization layers above and coupled to the first device and the subsequent device.

4. The process of claim 2 , wherein the transistor is a first device in a first region of the semiconductive substrate, the process further including:

forming a second device in a second region separate from the first device, wherein the first device is configured to operate at a voltage higher than the second device;

forming a third device in a third region separate from the first device and from the second device, wherein the first device is configured to operate at a voltage higher than the second device, and wherein the third device is configured to operate at a voltage lower than the second device; and

forming at least seven metallization layers above and coupled to the first device.

5. The process of claim 2 , wherein the transistor is a first device in a first region of the semiconductive substrate, the process further including:

forming a second device in a second region separate from the first device, wherein the first device is configured to operate at a voltage higher than the second device;

forming a third device in a third region separate from the first device and from the second device, wherein the first device is configured to operate at a voltage higher than the second device, and wherein the third device is configured to operate at a voltage lower than the second device;

forming a fourth device in a fourth region separate from the first device, from the second device, and from the third device, wherein the first device is configured to operate at a voltage higher than the second device, and wherein the third device is configured to operate at a voltage lower than the second device, wherein the fourth device is configured to operate a voltage lower than the third device; and

forming at least seven metallization layers above and coupled to the first device.

6. The process of claim 2 , wherein the transistor is a first device in a first region of the semiconductive substrate, the process further including:

forming a second device in a second region separate from the first device, wherein the first device is configured to operate at a voltage higher than the second device;

forming a third device in a third region separate from the first device and from the second device, wherein the first device is configured to operate at a voltage higher than the second device, and wherein the third device is configured to operate at a voltage lower than the second device;

forming a fourth device in a fourth region separate from the first device, from the second device, and from the third device, wherein the first device is configured to operate at a voltage higher than the second device, and wherein the third device is configured to operate at a voltage lower than the second device, wherein the fourth device is configured to operate a voltage lower than the third device;

forming a fifth device in a fifth region separate from the first device, from the second device, from the third device, and from the fourth device, wherein the first device is configured to operate at a voltage higher than the second device, and wherein the third device is configured to operate at a voltage lower than the second device, wherein the fourth device is configured to operate a voltage lower than the third device, and wherein the fifth device is configured to operate a voltage lower than the third device; and

forming at least seven metallization layers above and coupled to the first device.

7. The process of claim 2 , wherein the transistor is a first device in a first region of the semiconductive substrate, the process further including:

forming a subsequent device in a region separate from the first device, wherein the first device is configured to operate at a voltage higher than the subsequent device; and

assembling the first device and the subsequent device to a foundation substrate.

8. A process of forming an apparatus, comprising:

forming a gate upon a semiconductive substrate above a channel, wherein the semiconductive substrate includes a source implant at a gate first side, a drain implant at a gate second side, and a drain well that causes the apparatus to be asymmetrical about the first side and second side;

forming an interlayer dielectric layer (ILD0) above and on the source implant, the drain implant, the gate, and the drain well;

saliciding respective source and drain contact pads in the source- and drain implants, and below the ILD0 while the ILD0 is above and on the source implant, the drain implant, and the drain well;

forming respective source and drain contacts to complete a first device; and

forming a subsequent device in a region of the semiconductive substrate that is separate from the first device.

9. The process of claim 8 , further including forming seriatim metallizations above and on the ILD0, wherein the seriatim metallizations are coupled to the source- and drain contact pads.