IP Library › Granted Patent US 10,734,378

Granted Patent B2

US 10,734,378 · App. 16/080,914 · Granted Aug 4, 2020

Transistor threshold voltage variation optimization

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Quick Facts

Patent No.: US 10,734,378
App. No.: 16/080,914
Granted: Aug 4, 2020
Kind: B2

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Abstract

One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.

Claims (45)

1. An apparatus comprising:

a first transistor comprising a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a first plurality of layers;

wherein the first plurality of layers includes a work function material layer that includes at least one of: silver (Ag), gold (Au), cobalt (Co), molybdenum (Mo), ruthenium (Ru), tin (Sn), aluminum (Al), tungsten (W), platinum (Pt), and tantalum (Ta); and

wherein the first plurality of layers further includes another work function material layer that includes at least one of: graphene, metallic TMDs (transition metal dichalcogenide), NbS2 (niobium sulfur 2), VS2 (vanadium sulfur 2), WTe2 (tungsten tellurium 2), and TiSe2 (titanium selenium 2); and

a second transistor comprising a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a second plurality of layers,

wherein the second plurality of layers includes a work function material layer that includes at least one of: silver (Ag), gold (Au), cobalt (Co), molybdenum (Mo), ruthenium (Ru), tin (Sn), aluminum (Al), tungsten (W), platinum (Pt), and tantalum (Ta); and

wherein the second plurality of layers further includes another work function material layer that includes at least one of: graphene, metallic TMDs (transition metal dichalcogenide), NbS2 (niobium sulfur 2), VS2 (vanadium sulfur 2), WTe2 (tungsten tellurium 2), and TiSe2 (titanium selenium 2).

2. The apparatus of claim 1 , wherein each work function material layer is to optimize a threshold voltage variation between the first transistor and the second transistors, the optimized threshold voltage variation corresponding to a constant of proportionality (A VT ) of less than one millivolt-micrometer (mV-μm);

wherein A VT relates a standard deviation (σ VT ) of a distribution of threshold voltage values across a plurality of transistors and a transistor channel dimension.

3. The apparatus of claim 1 , wherein a film thickness of each work function material layer is in the range of 1 A (Angstrom) to 500 A.

4. The apparatus of claim 1 , wherein each work function material layer comprises an amorphous structure.

5. The apparatus of claim 1 , wherein each work function material layer comprises a crystal structure.

6. The apparatus of claim 5 , wherein the crystal structure is polycrystalline and a polycrystalline grain size is in the range of 10 A (Angstrom) to 500 A.

7. An integrated circuit comprising:

a first plurality of transistors of a first flavor; and

a second plurality of transistors of a second flavor comprising:

a first transistor comprising a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a first plurality of layers;

a second transistor comprising a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a second plurality of layers;

8. The integrated circuit of claim 7 , wherein each work function material layer is to optimize a threshold voltage variation between the first transistor and the second transistor, the optimized threshold voltage variation corresponding to a constant of proportionality (A VT ) of less than one millivolt-micrometer (mV-μm);

wherein A VT relates a standard deviation (σ VT ) of a distribution of threshold voltage values across a plurality of transistors and a transistor channel dimension.

9. The integrated circuit of claim 7 , wherein each of the first gate stack and the second gate stack comprises a plurality of work function material layers.

10. The integrated circuit of claim 7 , wherein a film thickness of each work function material layer is in the range of 1 A (Angstrom) to 500 A.

11. The integrated circuit of claim 7 , wherein each work function material layer comprises an amorphous structure.

12. The integrated circuit of claim 7 , wherein each work function material layer comprises a crystal structure.

13. The integrated circuit of claim 12 , wherein the crystal structure is polycrystalline and a polycrystalline grain size is in the range of 10 A (Angstrom) to 500 A.

14. A device comprising:

a controller;

a power source;

circuitry;

a first transistor comprising a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a first plurality of layers;

a second transistor comprising a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a second plurality of layers,

15. The device of claim 14 , wherein each work function material layer is to optimize a threshold voltage variation between the first transistor and the second transistor, the optimized threshold voltage variation corresponding to a constant of proportionality (A VT ) of less than one millivolt-micrometer (mV-μm);

wherein A VT relates a standard deviation (σ VT ) of a distribution of threshold voltage values across a plurality of transistors and a transistor channel dimension.

16. The device of claim 14 , wherein a film thickness of each work function material layer is in the range of 1 A (Angstrom) to 500 A.

17. The device of claim 14 , wherein each work function material layer comprises an amorphous structure.

18. The device of claim 14 , wherein each work function material layer comprises a crystal structure.

19. The device of claim 18 , wherein the crystal structure is polycrystalline and a polycrystalline grain size is in the range of 10 A (Angstrom) to 500 A.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022

From: INTEL CORPORATION

To: TAHOE RESEARCH, LTD.

Reel/Frame 061175/0176 →