Method and apparatus for improving stability of a 6T CMOS SRAM cell

1. A circuit comprising:

at least one access device, the at least one access device comprised of a non-planar transistor having a single fin;

at least one pull-up device, the at least one pull-up device comprised of a non-planar transistor having a single fin; and

at least one pull-down device, the at least one pull-down device comprised of a non-planar transistor having multiple fins.

2. The circuit of claim 1 , wherein the at least one pull-down device is comprised of a non-planar tri-gate transistor having two fins.

3. The circuit of claim 2 , wherein the two fins of the non-planar tri-gate transistor are located less than 60 nm from each other.

4. A CMOS SRAM cell comprising:

two access devices, each access device comprised of a tri-gate transistor having a single fin;

two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin;

two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins; and

wherein the CMOS SRAM cell has a cell ratio, a static noise margin (SNM), and a supply voltage.

5. The CMOS SRAM cell of claim 4 , wherein each pull-down device is comprised of a tri-gate transistor having two fins, each fin having a height and a width.

6. The CMOS SRAM cell of claim 5 , wherein the fins are located less than 60 nm from each other.

7. The CMOS SRAM cell of claim 5 , wherein the height of each fin is 60 nm.

8. The CMOS SRAM cell of claim 5 , wherein the width of each fin is 60 nm.

9. The CMOS SRAM cell of claim 4 , wherein each tri-gate transistor contains at least one corner, each corner having a radius of curvature of less than 10 nm.

10. The CMOS SRAM cell of claim 4 , wherein the cell ratio is greater than 2.0.

11. The CMOS SRAM cell of claim 4 , wherein the static noise margin (SNM) is greater than 240 mV.

12. The CMOS SRAM cell of claim 11 , wherein the supply voltage is less than 1.5 V.

13. A CMOS SRAM cell comprising:

two N-type access devices, each N-type access device comprised of a tri-gate transistor having a single fin;

two P-type pull-up devices, each P-type pull-up device comprised of a tri-gate transistor having a single fin;

two N-type pull-down devices, each N-type pull-down device comprised of a tri-gate transistor having multiple fins.

14. The CMOS SRAM cell of claim 13 , wherein each N-type pull-down device is comprised of a tri-gate transistor having two fins, each fin having a height and a width.

15. The CMOS SRAM cell of claim 14 , wherein the fins are located less than 60 nm from each other.