Methods of forming backside connections on a wafer stack
View Patent ↗Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.
1. A method comprising:
forming a first interconnect structure on one side of a first wafer;
forming a number of vias, each of the vias extending through the first interconnect structure and into the first wafer;
depositing a layer of insulating material over a surface of each of the number of vias;
depositing a sacrificial material on the insulating layer in each of the number of vias;
forming a second interconnect structure over the first interconnect structure, wherein the sacrificial material in each of the number of vias extends to one of a number of conductors in the second interconnect structure; and
bonding the first wafer to a second wafer to form a wafer stack.
2. The method of claim 1 , further comprising:
thinning an opposing side of the first wafer to expose the sacrificial material within each of the vias.
3. The method of claim 2 , further comprising performing alignment of the wafer stack using the exposed vias and sacrificial material.
4. The method of claim 2 , further comprising depositing a layer of dielectric material over the opposing side of the first wafer and the exposed vias.
5. The method of claim 4 , further comprising:
forming a number of other vias, each of the other vias extending through the dielectric layer and to the sacrificial material in one of the number of vias; and
removing the sacrificial material from each of the number of vias, wherein each of the vias extends to one of a number of conductors in the second interconnect structure.
6. The method of claim 5 , further comprising:
forming a number of trenches in the dielectric layer, each trench located coincident with one of the other vias; and
depositing a conductive material in each of the vias and each of the trenches, the conductive material in each of the trenches forming a land.
7. The method of claim 6 , wherein the conductive material comprises a copper material.
8. The method of claim 6 , further comprising depositing a connection element on each of the lands.
9. The method of claim 6 , further comprising continuing deposition of the conductive material to form connection elements proximate at least some of the trenches.
10. The method of claim 5 , further comprising depositing a conductive material in each of the vias.
11. The method of claim 10 , wherein the conductive material comprises a copper material.
12. The method of claim 10 , further comprising continuing deposition of the conductive material to form connection elements proximate at least some of the vias.
13. The method of claim 5 , wherein the sacrificial material comprises one of a glass material and a polymer material.
14. The method of claim 5 , wherein removing the sacrificial material comprises performing an etching process.
15. The method of claim 14 , wherein the etching process is performed using a solution that removes the sacrificial material at a faster rate than the dielectric material.
16. The method of claim 1 , further comprising:
etching an opposing side of the first wafer to expose the layer of insulating material in each of the vias.
17. The method of claim 16 , further comprising performing alignment of the wafer stack using the exposed vias and insulating material.
18. The method of claim 16 , further comprising depositing a layer of dielectric material over the opposing side of the first wafer and the exposed insulating material.
19. The method of claim 18 , further comprising:
forming a number of trenches in the dielectric layer and the exposed insulating material to expose the sacrificial material; and
removing the sacrificial material from each of the number of vias, wherein each of the vias extends to one of a number of conductors in the second interconnect structure.
20. The method of claim 19 , further comprising depositing a conductive material in each of the vias and each of the trenches.
21. The method of claim 20 , wherein the conductive material in each of the trenches forms a land, the method further comprising depositing a connection element on each of the lands.
22. The method of claim 20 , further comprising continuing deposition of the conductive material to form connection elements proximate at least some of the trenches.
23. The method of claim 1 , wherein the insulating material comprises one of an oxide material, a nitride material, and a carbide material.
24. The method of claim 23 , wherein the insulating material comprises one of SiO 2 , Si 3 N 4 , and SiC.
25. The method of claim 1 , further comprising cutting the wafer stack into a plurality of stacked die.
26. The method of claim 25 , further comprising packaging one of the stacked die to form a packaged integrated circuit device.
27. The method of claim 1 , further comprising forming at least one dummy via extending through the first interconnect structure and into the first wafer.
28. A method comprising:
forming a first interconnect structure on one side of a first wafer;
forming a number of vias, each of the vias extending through the first interconnect structure and into the first wafer;
depositing a layer of insulating material over a surface of each of the number of vias;
depositing a conductive material on the insulating layer in each of the number of vias;
forming a second interconnect structure over the first interconnect structure, wherein the conductive material in each of the number of vias extends to one of a number of conductors in the second interconnect structure; and
bonding the first wafer to a second wafer to form a wafer stack.
29. The method of claim 28 , further comprising:
thinning an opposing side of the first wafer to expose the conductive material within each of the vias.
30. The method of claim 29 , further comprising performing alignment of the wafer stack using the exposed vias and conductive material.
31. The method of claim 29 , further comprising depositing a layer of dielectric material over the opposing side of the first wafer and the exposed vias.
32. The method of claim 31 , further comprising forming a number of other vias, each of the other vias extending through the dielectric layer and to the conductive material in one of the number of vias.
33. The method of claim 32 , further comprising:
forming a number of trenches in the dielectric layer, each trench located coincident with one of the other vias; and
depositing a conductive material in each of the other vias and each of the trenches, the conductive material in each of the trenches forming a land.
34. The method of claim 33 , wherein the conductive material in each of the vias and the conductive material in each of the other vias comprises a copper material.
35. The method of claim 33 , further comprising depositing a connection element on each of the lands.
36. The method of claim 33 , further comprising continuing deposition of the conductive material to form connection elements proximate at least some of the trenches.
37. The method of claim 32 , further comprising depositing a conductive material in each of the other vias.
38. The method of claim 37 , wherein the conductive material in each of the vias and the conductive material in each of the other vias comprises a copper material.
39. The method of claim 37 , further comprising continuing deposition of the conductive material to form connection elements proximate at least some of the other vias.
40. The method of claim 28 , further comprising:
etching an opposing side of the first wafer to expose the layer of insulating material in each of the vias.
41. The method of claim 40 , further comprising performing alignment of the wafer stack using the exposed vias and insulating material.
42. The method of claim 40 , further comprising depositing a layer of dielectric material over the opposing side of the first wafer and the exposed insulating material.
43. The method of claim 42 , further comprising forming a number of trenches in the dielectric layer and the exposed insulating material to expose the conductive material in the vias.
44. The method of claim 43 , further comprising depositing a conductive material in each of the vias and each of the trenches.
45. The method of claim 44 , wherein the conductive material in each of the trenches forms a land, the method further comprising depositing a connection element on each of the lands.
46. The method of claim 44 , further comprising continuing deposition of the conductive material to form connection elements proximate at least some of the trenches.
47. The method of claim 28 , wherein the insulating material comprises one of an oxide material, a nitride material, and a carbide material.
48. The method of claim 47 , wherein the insulating material comprises one of SiO 2 , Si 3 N 4 , and SiC.
49. The method of claim 28 , further comprising cutting the wafer stack into a plurality of stacked die.
50. The method of claim 49 , further comprising packaging one of the stacked die to form a packaged integrated circuit device.
51. The method of claim 28 , further comprising forming at least one dummy via extending through the first interconnect structure and into the first wafer.