Memory including bipolar junction transistor select devices
View Patent ↗An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.
1. A method comprising:
forming a plurality of bipolar junction select transistors for a memory array;
forming a shared control region in a semiconductor body for said transistors; and
forming, on said body, a plurality of biasing structures to modify a charge distribution in said control region.
2. The method of claim 1 including implanting first regions in said shared control region, laterally to said biasing structures.
3. The method of claim 2 including forming, in the shared control region, control contact portions for said transistors.
4. The method of claim 3 including forming a common conduction region of a first conductivity type, the shared control region of a second conductivity type and a first doping level, the first regions of said first conductivity type, and the control contact portions are of said second conductivity type.
5. The method of claim 2 including forming contact portions of a second doping level, higher than said first doping level.
6. The method of claim 3 wherein forming a biasing structures including depositing a polysilicon layer on a gate insulator and defining said polysilicon layer to form polysilicon strips.