Multi-core shared page miss handler

1. A system comprising:

a plurality of requesting devices including a plurality of processor cores; a plurality of operating systems running simultaneously within the system to control the plurality of requesting devices:

an interconnect to couple together the plurality of processor cores; a page miss request queue to receive a page miss request for a respective miss in a translation lookaside buffer (TLB) of each of the plurality of requesting devices;

arbitration logic to identify a first page miss request of a plurality of page miss requests to process;

a single, shared page miss handler (PMH) to perform a page table walk to generate a physical address responsive to the first page miss request;

wherein the PMH is further to eliminate a duplicate page table walk and a duplicate page fault of the first page miss request; and

communication logic to, when the page table walk does not result in a fault, send the physical address to an operating system for a corresponding requesting device, and, otherwise, when the page table walk does result in a fault, send a fault signal to the operating system for the corresponding requesting device responsive to the first page miss request.

2. The system of claim 1 , further comprising logic to signal a fault for the corresponding requesting device responsive to the first page miss request.

3. The system of claim 1 , further comprising a TLB coupled with the PMH to store the physical address after the page table walk.

4. The system of claim 1 , wherein the plurality of requesting devices further comprises a graphics processor.

5. The system of claim 1 , wherein the plurality of requesting devices further comprises a transport processor.

6. The system of claim 1 , wherein the plurality of requesting devices further comprises a security processor.

7. The system of claim 1 , wherein the plurality of requesting devices further comprises a video device.

8. The system of claim 1 , further comprising a connectivity device coupled to the plurality of processor cores.

9. The system of claim 1 , further comprising a serial bus coupled to the plurality of processor cores.

10. The system of claim 1 , further comprising a modem device coupled to the plurality of processor cores.

11. The system of claim 1 , further comprising a memory controller coupled to the single, shared page miss handler.

12. The system of claim 1 , further comprising an I/O expansion device coupled to the plurality of processor cores.

13. The system of claim 1 , further comprising a solid state drive coupled to the plurality of processor cores.

14. A method comprising:

executing instructions with a plurality of processor cores, the plurality of processor cores controlled by a plurality of operating systems running simultaneously within a single computer:

coupling the plurality of processor cores together with an interconnect; receiving a page miss request in a page miss request queue for a respective miss in a translation lookaside buffer (TLB) of each of a plurality of requesting devices including the plurality of processor cores;

identifying a first page miss request of a plurality of page miss requests to process; performing a page table walk with a single, shared page miss handler (PMH) to generate a physical address responsive to the first page miss request;

wherein the PMH is further to eliminate a duplicate page table walk and a duplicate page fault of the first page miss request; and

sending, when the page table walk does not result in a fault, sending the physical address to an operating system for a corresponding requesting device, and, otherwise, when the page table walk does result in a fault, sending a fault signal to the operating system for the corresponding requesting device responsive to the first page miss request.

15. The method of claim 14 , further comprising signaling a fault for the corresponding requesting device responsive to the first page miss request.

16. The method of claim 14 , further comprising storing the physical address after the page table walk in a TLB coupled with the PMH.

17. The method of claim 14 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a graphics processor of the plurality of requesting devices.

18. The method of claim 14 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a transport processor of the plurality of requesting devices.

19. The method of claim 14 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a security processor of the plurality of requesting devices.

20. The method of claim 14 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a video device of the plurality of requesting devices.

21. The method of claim 14 , further comprising coupling the plurality of processor cores to a connectivity device.

22. The method of claim 14 , further comprising coupling the plurality of processor cores to a serial bus.

23. The method of claim 14 , further comprising coupling the plurality of processor cores to a modem device.

24. The method of claim 14 , further comprising coupling the plurality of processor cores to a memory controller.

25. The method of claim 14 , further comprising coupling the plurality of processor cores to an I/O expansion device.