Space transformer
View Patent ↗An apparatus including a planar semiconductor substrate including a plurality of devices and a first pattern of electrical contacts formed on the first surface of the semiconductor substrate; and a plurality of layers of conductive material alternating between dielectric material on the first surface of the semiconductor substrate, the plurality of layers of conductive material including a wiring layer including a second pattern of electrical contacts, wherein the second surface of the semiconductor substrate includes openings to the first pattern of electrical contacts. A method including forming a space transformer including a semiconductor substrate including, on a device side, a device region, a first pattern of electrical contacts, and at least one routing layer and a pad layer including a second pattern of electrical contacts; and forming openings through the space transformer to the first pattern of electrical contacts on the semiconductor substrate.
1. An apparatus comprising:
a planar semiconductor substrate comprising a plurality of devices comprising transistors formed therein and a first pattern of electrical contacts formed on a first surface of the semiconductor substrate; and
a plurality of layers of conductive material alternating between dielectric material on the first surface of the semiconductor substrate, the plurality of layers of conductive material comprising a wiring layer comprising a second pattern of electrical contacts,
wherein a second surface of the semiconductor substrate comprises openings to the first pattern of electrical contacts.
2. The apparatus of claim 1 , wherein the first pattern of electrical contacts comprises a first pitch and the second plurality of contacts comprise a second pitch and the first pitch is greater than the second pitch.
3. The apparatus of claim 1 , wherein the plurality of devices are operable to perform a task related to at least one of high speed input/output, radio frequency, or power delivery.
4. The apparatus of claim 1 , wherein the thickness of the semiconductor substrate comprises less than about 25 microns.
5. The apparatus of claim 1 , further comprising at least one of a diffusion barrier layer and an insulation layer disposed on the second surface of the semiconductor substrate.
6. The apparatus of claim 1 , wherein the semiconductor substrate comprises a narrow band gap semiconductor material including silicon.
7. The apparatus of claim 1 , wherein the semiconductor substrate comprises a wide band gap semiconductor material.
8. The apparatus of claim 1 , further comprising a die coupled to one of the first pattern of electrical contacts and the second pattern of electrical contacts.
9. An apparatus, comprising:
a space transformer comprising a semiconductor substrate comprising on a first side thereof:
a plurality of devices comprising transistors formed in the substrate,
a first pattern of electric contacts, and
a plurality of layers of conductive material alternating between dielectric material, the plurality of layers of conductive material comprising a wiring layer comprising a second pattern of electrical contacts; and
at least one integrated circuit chip mounted on one of the first side and the second side of the semiconductor substrate.
10. The apparatus of claim 9 , wherein a second side of the semiconductor substrate comprises openings to the first pattern of electrical contacts.
11. The apparatus of claim 9 , wherein the first pattern of electrical contacts comprises a first pitch and the second pattern of contacts comprise a second pitch and the first pitch is greater than the second pitch.
12. The apparatus of claim 9 , wherein the plurality of devices are operable to perform a task related to at least one of high speed input/output, radio frequency, or power delivery.
13. The apparatus of claim 9 , wherein the thickness of the semiconductor substrate comprises less than about 25 microns.
14. The apparatus of claim 9 , further comprising at least one of a diffusion barrier layer and an insulation layer disposed on a second surface of the semiconductor substrate.
15. The apparatus of claim 9 , wherein the semiconductor substrate comprises a narrow band gap semiconductor material including silicon.
16. The apparatus of claim 9 , wherein the semiconductor substrate comprises a wide band gap semiconductor material.
17. The apparatus of claim 9 , further comprising a package substrate coupled to the other of the first side and the second side of the semiconductor substrate.
18. A method comprising:
forming a space transformer comprising a semiconductor substrate comprising on a device side, a device region comprising devices comprising transistors formed in the semiconductor substrate, a first pattern of electrical contacts, and at least one routing layer and a pad layer comprising a second pattern of electrical contacts; and
forming openings through the space transformer to the first pattern of electrical contacts on the semiconductor substrate.
19. The method of claim 18 , further comprising forming a barrier layer on the semiconductor substrate.
20. The method of claim 18 , further comprising forming solder bumps on the first pattern of electrical contacts.
21. The method of claim 20 , further comprising coupling the solder bumps to contacts of a package.
22. The method of claim 18 , further comprising coupling an integrated circuit chip to one of the first pattern of electrical contacts and the second pattern of electrical contacts.