IP Library Granted Patent US 10,446,499
Granted Patent B2
US 10,446,499 · App. 15/438,321 · Granted Oct 15, 2019

High density interconnect device and method

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Quick Facts
Patent No.
US 10,446,499
App. No.
15/438,321
Granted
Oct 15, 2019
Kind
B2
Abstract

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

Claims (26)

1. A method of assembling an interconnect device, comprising:

assembling a first die and a second die to an interconnecting bridge, wherein

the interconnecting bridge has a plurality of high density interconnects with a first bump pitch;

wherein the first die has three connection regions including high density interconnects with the first bump pitch along a side of the first die;

wherein the first die includes a connection region around remaining sides of the first die;

wherein the first die includes a connection region located centrally on the first die;

wherein the second die includes two connection regions including high density interconnects with the first bump pitch;

wherein the second die includes a connection region with a bump pitch different from the high density interconnects with the first bump pitch;

assembling the first die to a circuit board;

removing a release layer and a buildup layer in the circuit board to form a recess; and

locating the interconnecting bridge to reside in the recess.

2. The method of claim 1 , further including assembling the second die to a circuit board.

3. The method of claim 1 , further including assembling the second die to the circuit board.

4. The method of claim 1 , further including:

placing the first die and the second die in a carrier by orienting the high density interconnects for the first die and the second die toward each other; and

bonding the interconnecting bridge to the first die and the second die by a process selected from solder reflow and thermocompression bonding.

5. The method of claim 1 , further including:

placing the first die and the second die in a carrier by orienting the high density interconnects for the first die and the second die toward each other;

bonding the interconnecting bridge to the first die and the second die by a process selected from solder reflow and thermocompression bonding; and

assembling the second die to the circuit board.

6. The method of claim 1 , further including assembling the second die to the circuit board, further:

wherein the circuit board has a bump pitch region to match the first bump pitch of the first die, a bump pitch;

wherein the circuit board has a bump pitch region to match the connection region around remaining sides of the first die;

wherein the circuit board has a bump pitch region to match the connection region located centrally on the first die;

wherein the circuit board has a bump pitch region to match the high density interconnects of the second die; and

wherein the circuit board has a bump pitch region to match the second die with a bump pitch different from the high density interconnects with the first bump pitch.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →