Folded semiconductor package architectures and methods of assembling same
A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
1. A semiconductor package substrate, comprising:
a die side and a land side;
a fold in the semiconductor package substrate, wherein a first portion of the land side and a subsequent portion of the land side are mated;
a first embedded device disposed within the first portion, wherein the first embedded device exhibits orthogonal electrical coupling through the first portion with at least one via,
beginning at the semiconductor package substrate die side at the subsequent portion, through the first portion, and terminating at the first embedded device;
a fold in the semiconductor package substrate, wherein a second portion of the land side and a fourth portion of the land side are mated;
a second embedded device disposed within the second portion, wherein the second embedded device exhibits orthogonal electrical coupling through the second portion with at least one via, beginning at the semiconductor package substrate die side at the fourth portion, through the second portion, and terminating at the second embedded device; and
a semiconductive device disposed on the die side, wherein the orthogonal electrical coupling from the first embedded device further orthogonally couples to the semiconductive device, and wherein the orthogonal electrical coupling from the second embedded device further orthogonally couples to the semiconductive device.
2. The semiconductor package substrate of claim 1 , further including:
a virtual recess on the land side, formed at a first end of the semiconductor package substrate that includes the first portion and at a second end of semiconductor package substrate that includes the second portion.
3. The semiconductor package substrate of claim 2 , further including a passive device seated in the virtual recess upon the land side.
4. The semiconductor package substrate of claim 1 , wherein a first end of the semiconductor package substrate includes the first portion, and wherein the first end of the semiconductor package substrate abuts a portion of the land side.
5. The semiconductor package substrate of claim 4 ,
wherein a second end of the semiconductor package substrate includes the second portion, and wherein the second end abuts a portion of the land side.
6. The semiconductor package substrate of claim 5 , further including a passive device seated on the land side between the first end and the second end.
7. The semiconductor package substrate of claim 5 , wherein the fold including the first portion is longer than the fold including the second portion.
8. The semiconductor package substrate of claim 5 , wherein the fold including the first portion and the fold including the second portion are symmetrical.
9. The semiconductor package substrate of claim 1 , further including a board, wherein the semiconductor package substrate first portion is seated on the board by the die side.
10. The semiconductor package substrate of claim 9 , wherein the first portion is seated within a recess within the board.
11. The semiconductor package substrate of claim 9 , further including:
wherein the first portion is seated within a first recess within the board; and
wherein the second portion is seated within a second recess within the board.
12. The semiconductor package substrate of claim 9 ,
wherein the semiconductor package substrate first and second portions are seated on the board by the die side.