IP Library Granted Patent US 9,202,803
Granted Patent B2
US 9,202,803 · App. 14/229,734 · Granted Dec 1, 2015

Laser cavity formation for embedded dies or components in substrate build-up layers

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Quick Facts
Patent No.
US 9,202,803
App. No.
14/229,734
Granted
Dec 1, 2015
Kind
B2
Abstract

An apparatus including a package substrate including a plurality of layers of conductive material, the package substrate including a cavity; and a device in the cavity, wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points of the device. An apparatus including a package substrate comprising a plurality of conductive layers and a silicon bridge die disposed between ones of the plurality of conductive layers and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the silicon bridge die; and a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers.

Claims (20)

1. An apparatus comprising:

a package substrate comprising a plurality of layers of conductive material; and

a silicon bridge die comprising a contact side and a back side, wherein the back side of the silicon bridge die is coupled to the package at an antepenultimate layer of the plurality of layers of conductive material and wherein the silicon bridge die is disposed between a penultimate layer and an ultimate layer of the plurality of layers of conductive material and wherein the contact side oriented in a direction of the ultimate layer of the plurality of layers of conductive material,

wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points on the device side of the silicon bridge die.

2. The apparatus of claim 1 , further comprising a dielectric material between the ultimate layer of the plurality of layers of conductive material and the device.

3. The apparatus of claim 1 , wherein the package substrate further comprises a plurality of dielectric layers respective ones of which are disposed between the plurality of layers of conductive material.

4. The apparatus of claim 1 , wherein the ultimate layer of the plurality of layers of conductive material define contact points, the apparatus further comprising a first die connected to a first one of the contact points and a second die connected to a second one of the contact points.

5. The apparatus of claim 4 , wherein the first die comprises a logic die and the second die comprises a memory die.

6. The apparatus of claim 1 , wherein the ultimate layer of the plurality of layers of conductive material defines contact points, the apparatus further comprising a surface finish on the contact points.

7. The apparatus of claim 1 , wherein the plurality of conductive layers are disposed on a first side of the core substrate, the apparatus further comprising contact points on a second side of the core substrate, wherein the contact points are coupled to interconnections on the first side of the core substrate.

8. An apparatus comprising:

a package substrate comprising a plurality of conductive layers and a die comprising a contact side and a back side, wherein the back side of the die is coupled at an antepenultimate layer of the plurality of conductive layers and disposed between a penultimate and an ultimate layer of the plurality of conductive layers.

9. The apparatus of claim 8 , wherein an ultimate layer of the plurality of conductive layers defines contacts to contact points of the device.

10. The apparatus of claim 8 , wherein the ultimate layer of the plurality of conductive layers defines contact points.

11. The apparatus of claim 10 , wherein the package substrate comprises a core substrate and the plurality of conductive layers are disposed on a first side of the core substrate and the package substrate further comprises a plurality of contact points on a second side of core substrate.

12. An apparatus comprising

a package substrate comprising a plurality of conductive layers and a silicon bridge die coupled at a antepenultimate layer of the plurality of conductive layers and disposed between the penultimate layer and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the device side of the silicon bridge die; and

a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers.

13. The apparatus of claim 12 , wherein the logic die is coupled to ones of the contact points of the ultimate layer of the plurality of conductive layers, the apparatus further comprising a memory die coupled to other contact points of the ultimate layer of the plurality of conductive layers.

14. The apparatus of claim 12 , wherein the package substrate comprises a core substrate and the plurality of conductive layers are disposed on a first side of the core substrate and the package substrate further comprises a plurality of contact points on a second side of core substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2014
From: ZHANG, CHONG; LOTZ, STEFANIE M.; ZHANG, QINGLEI; BOYAPATI, SRI RANGA; SHARMA, NIKHIL; SALAMA, ISLAM A.
To: INTEL CORPORATION
Reel/Frame 032727/0009 →