Low speed access to DRAM
View Patent ↗Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
1. A memory apparatus comprising:
a differential receiver coupled to a protocol recognition circuit;
a low speed receiving circuit comprising:
a first receiver coupled with a first input of the differential receiver;
a second receiver coupled with a second input of the differential receiver; and,
the low speed receiving circuit also coupled with the protocol recognition circuit, the first and second receivers to access the protocol recognition block at a lower frequency than the differential receiver.
2. The apparatus of claim 1 , comprising an internal register coupled to the protocol recognition block, the low speed receiving circuit to provide access to the internal register.
3. The apparatus of claim 1 , comprising logic coupled to the protocol recognition block, the low speed receiving circuit to provide access to the logic.
4. The apparatus of claim 3 , wherein the logic includes a memory array.
5. The apparatus of claim 4 , wherein the memory array is a DRAM.
6. A system comprising:
a memory apparatus comprising:
a differential receiver coupled to a protocol recognition circuit;
a low speed receiving circuit comprising a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, the low speed receiving circuit coupled with the protocol recognition circuit, the first and second receivers to access the protocol recognition block; and
a display device coupled with the memory apparatus, the display device to display information from the memory.
7. The system of claim 6 , wherein the memory apparatus comprises an internal register coupled to the protocol recognition block, the low speed receiving circuit to provide access to the internal register.
8. The system of claim 6 , wherein the memory apparatus comprises logic coupled to the protocol recognition block, the low speed receiving circuit to provide access to the logic.
9. The system of claim 8 , wherein the logic includes a memory array.
10. The system of claim 9 , wherein the memory array is a DRAM.