RECESSED AND EMBEDDED DIE CORELESS PACKAGE
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.
1 - 6 . (canceled)
7 . A package structure, comprising:
a dielectric material, wherein the dielectric material includes a first surface, a second surface that is spaced apart from the first surface, and a protruding portion that projects from the first surface and includes the second surface; and
a die at least partially disposed in the dielectric material, and is at least partially embedded in the protruding portion of the dielectric material.
8 . The package structure of claim 7 , wherein the first surface is parallel the second surface.
9 . The package structure of claim 7 , wherein the die is attached to the dielectric material with an adhesive film.
10 . The package structure of claim 7 , wherein the package structure is a first package structure, wherein the package structure includes a second package structure, wherein the first and second package structures are coupled together in a package-on-package (PoP) configuration.
11 . The package structure of claim 10 , wherein the first package structure includes one or more interconnects comprising vias with contact pads, to provide electric coupling with the second package structure.
12 . The package structure of claim 11 , wherein the one or more interconnects are first interconnects, wherein the second package structure includes one or more second interconnects to couple with respective ones of the first interconnects.
13 . The package structure of claim 12 , further comprising one or more third interconnects formed in a die area of the first package structure, to provide electrical connectivity between the die and other components of the package structure or another apparatus.
14 . The package structure of claim 7 , wherein the protruding portion further includes at least one side connecting the first and second surfaces, to form, at least in part, the protruding portion, wherein an angle between the at least one side and a plane of the second surface is about 70 degree or less.
15 . The package structure of claim 7 , wherein the package structure comprises a coreless package.
16 . A method for providing a package structure, comprising:
forming a cavity in a plating material of the package structure;
attaching a die inside the cavity;
disposing a dielectric material to at least partially cover the die inside the cavity;
removing at least a portion of the plating material, wherein removing includes exposing a first surface of the dielectric material, and exposing, at least in part, a second surface of the dielectric material, the second surface being spaced apart from the first surface, to form a protruding portion of the dielectric material that projects from the first surface and includes the second surface, wherein the die is at least partially housed in the protruding portion of the dielectric material.
17 . The method of claim 16 , further comprising: providing one or more interconnect structures inside the dielectric material.
18 . The method of claim 17 , wherein providing interconnect structures includes forming one or more vias with contact pads, wherein forming the one or more vias with contact pads includes disposing the contact pads on the first surface of the dielectric material.
19 . The method of claim 18 , wherein removing at least a top portion of the packaging layer further includes exposing the contact pads, to provide electric coupling with another package structure.
20 . The method of claim 16 , wherein the attaching a die inside the cavity includes disposing the die in the cavity using an adhesive film.
21 . The method of claim 16 , wherein the forming a cavity in a plating material includes etching the plating material to form a top portion, a bottom portion, and an angled portion of the cavity, wherein the angled portion connects the top and bottom portion, wherein the attaching the die inside the cavity includes adhering the die to the top portion of the cavity.
22 . The method of claim 16 , wherein the disposing a dielectric material to at least partially cover the die inside the cavity includes forming the dielectric material on the plating material, adjacent the die inside the cavity, to fill a portion of the cavity that is left free after attaching the die inside the cavity.
23 . The method of claim 16 , wherein exposing the first and second surfaces includes providing the second surface parallel the first surface.
24 . A computer system, comprising:
a processor; and
a memory device communicatively coupled with the processor, wherein at least one of the processor or memory device comprises an integrated circuit (IC) package having a dielectric material, wherein the dielectric material includes a first surface, a second surface that is spaced apart from the first surface, and a protruding portion that projects from the first surface and includes the second surface; and a die at least partially disposed in the dielectric material, and is at least partially embedded in the protruding portion of the dielectric material.
25 . The computer system of claim 24 , wherein the IC package comprises a coreless package.
26 . The computer system of claim 24 , wherein the IC package comprises a first IC package, wherein the computer system includes a second IC package, wherein the first and second IC package structures comprise respective coreless package structures and are coupled together in a package-on-package (PoP) configuration.
27 . The computer system of claim 26 , wherein the first and second IC package structures include respective one or more interconnects, to provide electrical coupling of the first and second IC packages in the PoP configuration.