Forming functionalized carrier structures with coreless packages
View Patent ↗Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
1. A method comprising;
forming a carrier material comprising a top layer and a bottom layer separated by an etch stop layer;
etching a cavity through the bottom layer to expose the etch stop layer;
attaching a die to the etch stop layer within the cavity;
forming a dielectric material adjacent the die and on the bottom layer of the carrier material;
forming die pad interconnect structures in the die area;
forming vias in a non-die area to connect with the bottom layer carrier material;
forming a coreless substrate by building up layers on the dielectric material; and
removing the entire top layer carrier material and the entire etch stop layer from the bottom layer carrier material.
2. The method of claim 1 further comprising patterning the bottom layer carrier material to form at least one of an inductor and a PoP land structure.
3. The method of claim 1 further comprising wherein the bottom layer carrier material is attached to the coreless package without an adhesive.
4. The method of claim 1 wherein the coreless substrate comprises a portion of a coreless, bumpless, build up layer package.
5. The method of claim 4 further comprising wherein a top surface of the PoP land structure is coplanar with a top surface of the coreless, bumpless, build up layer package.