Floating body memory array
View Patent ↗Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
1. A chip, comprising:
an array of floating body cells each consisting of a single transistor having a channel and a gate to control conduction in the channel, the array comprising conductive signal lines to controllably apply an impact ionization potential across a selected cell′s channel without applying said impact ionization potential to unselected cells.
2. The chip of claim 1 , in which the conductive signal lines comprise bit lines coupled to sources of the cells and source lines coupled to drains in the cells, the bit and source lines being separately selectably coupleable to two or more different voltage levels.
3. The chip of claim 2 , in which adjacent pairs of cells share a common source line but have different bit lines.
4. The chip of claim 3 , in which the adjacent pairs of cells share a common wordline coupled to their gates.
5. The chip of claim 2 , in which adjacent pairs of cells share a common bit line but have different source lines.
6. The chip of claim 5 , in which the adjacent pairs of cells share a common wordline coupled to their gates.
7. The chip of claim 1 , in which the impact ionization potential is in excess of 1.5 V.
8. The chip of claim 1 , in which each cell has two or more gates.
9. The chip of claim 1 , in which the cells are arranged into rows and columns with cells in a common column sharing a common source and wordline but adjacent cells in said common column having different bit lines.
10. A memory, comprising:
a plurality of floating body cells arranged in rows and columns and each consisting of a single transistor having a gate and a channel;
a set of first conductors coupled to channels of cells in pairs of adjacent rows; and
a set of second conductors each coupled to channels of alternating cells in a common column, wherein a potential, sufficient to write a value, can be applied across a selected channel without imposing said potential to unselected channels.
11. The memory of claim 10 , in which the set of first conductors are coupled to cell sources, and the set of second conductors are coupled to cell drains.
12. The memory of claim 10 , in which the set of first conductors are coupled to cell drains, and the set of second conductors are coupled to cell sources.
13. The memory of claim 10 , in which each cell has two or more gates.
14. The memory of claim 10 , comprising a set of third conductors each coupled to gates of cells in a common row.
15. The memory of claim 10 , in which the potential sufficient for writing a value is in excess of 1.5 V.
16. A system, comprising:
(a) a microprocessor comprising a an array of floating body cells each consisting of a single transistor having a channel and a gate to control conduction in the channel, the array comprising conductive signal lines to controllably apply an impact ionization potential across a selected cell′s channel without applying said impact ionization potential to unselected cells; (b) an antenna; and (c) a wireless interface coupled to the microprocessor and to the antenna to communicatively link the microprocessor to a wireless network.
17. The system of claim 16 , in which the conductive signal lines comprise bit lines coupled to drains of the cells and source lines coupled to sources in the cells, the bit and source lines being separately selectably coupleable to two or more different voltage levels.
18. The system of claim 17 , in which adjacent pairs of cells share a common source line but have different bit lines.
19. The system of claim 18 , in which the adjacent pairs of cells share a common wordline coupled to their gates.
20. The system of claim 17 , in which adjacent pairs of cells share a common bit line but have different source lines.
21. A method, comprising:
writing data into a line of floating body cells, the act of writing comprising first writing a ′0 into all cells in the line and then writing a ′1 into selected cells within the line, wherein a negative impact ionization voltage is applied from source to bit lines of the line of cells when the ′0 is written into the cells, and a positive impact ionization voltage is applied from the source to bit lines of the line of cells when a ′1 is written into the selected cells.