Method to integrate ARM ecosystem IPs into PCI-based interconnect
View Patent ↗Methods and apparatus for integrating ARM-based IPs in computer system employing PCI-based fabrics. An PCI-based fabric is operatively coupled to an ARM-based ecosystem employing an ARM-based fabric such as OCP, AHB, or BVCI via a corresponding fabric-to-fabric bridge. Transactions between IP operatively coupled to the PCI-based fabric and IP in the ARM-based ecosystem are facilitated by applying applicable ordering and conversions operations via the fabric-to-fabric bridge and/or fabrics. For example, posted writes originating from IP coupled to the PCI-based fabric are converted to non-posted writes and serialized via the fabric-to-fabric bridge and forwarded to the ARM-based ecosystem.
1. An apparatus comprising:
a first fabric comprising a Peripheral Component Interconnect (PCI)-based fabric to which a first plurality of Intellectual Property (IP) blocks are coupled;
a second fabric comprising one of an Open Core Protocol (OCP) or an Advanced Microcontroller Bus Architecture (AMBA)-based fabric to which a second plurality of IP blocks are coupled; and
a fabric-to-fabric bridge configured to facilitate transfer of data between the first fabric and the second fabric and configured to convert a posted memory write transaction originating from the first fabric into a non-posted memory write transaction and serialize the non-posted memory write transaction upon forwarding the transaction towards the second fabric.
2. The apparatus of claim 1 , wherein the fabric-to-fabric bridge is further configured to serialize read returns towards the second fabric, wherein the fabric-to-fabric bridge does not return read data to the second fabric until a previous non-posted write towards the first fabric completes.
3. The apparatus of claim 1 , wherein the fabric-to-fabric bridge is further configured to convert a non-posted memory write transaction into a posted transaction and forward the posted transaction to the first fabric.
4. The apparatus of claim 1 , wherein the fabric-to-fabric bridge is further configured to push posted memory writes from the second fabric to ensure read completion from the second fabric.
5. The apparatus of claim 1 , further comprising at least one ARM-based processor core, operatively coupled to the second fabric.
6. The apparatus of claim 1 , further comprising at least one x86-based processor core operatively coupled to the first fabric.
7. The apparatus of claim 6 , wherein the apparatus further comprises:
a coherent fabric to which a plurality of x86-based processor cores are coupled; and
a bridge, coupled between the PCI-based fabric and the coherent fabric.
8. The apparatus of claim 1 , further comprising a third fabric coupled to the second fabric, the third fabric comprising one of a secondary OCP fabric or a secondary AMBA-based fabric.
9. The apparatus of claim 1 , wherein the fabric-to-fabric bridge includes:
a first First-in First out (FIFO) buffer comprising a downward command queue; and
a second FIFO buffer comprising a downward data queue.
10. The apparatus of claim 9 , wherein the fabric-to-fabric bridge includes:
a third FIFO buffer comprising an upward command queue; and
a fourth FIFO buffer comprising an upward data queue.
11. The apparatus of claim 10 , wherein the fabric-to-fabric bridge further comprises a clock crossing domain.
12. The apparatus of claim 1 , wherein the second fabric comprises an OCP fabric and the apparatus comprises:
a PCI ordering domain;
a First-in First-out (FIFO) ordering domain; and
an OCP ordering domain.
13. A computing device, comprising:
a main board on which a plurality of components are mounted or operatively coupled, the plurality of components including,
a communications chip; and
a System on a Chip (SoC), comprising,
a first fabric comprising a Peripheral Component Interconnect (PCI)-based fabric to which a first plurality of Intellectual Property (IP) blocks are coupled;
a second fabric comprising one of an Open Core Protocol (OCP) or an Advanced Microcontroller Bus Architecture (AMBA)-based fabric to which a second plurality of IP blocks are coupled; and
a fabric-to-fabric bridge configured to facilitate transfer of data between the first fabric and the second fabric and configured to convert a posted memory write transaction originating from the first fabric into a non-posted memory write transaction and serialize the non-posted memory write transaction while forwarding the transaction towards the second fabric,
wherein one of the first and second plurality of IP blocks further comprises a communication interface coupled to the communication chip via wiring in the main board.
14. The computing device of claim 13 , wherein the fabric-to-fabric bridge is further configured to serialize read returns towards the second fabric, wherein the fabric-to-fabric bridge does not return read data to second fabric until a previous non-posted write towards the first fabric completes.
15. The computing device of claim 13 , wherein the fabric-to-fabric bridge is further configured to convert a non-posted memory write transaction into a posted transaction and forward the posted transaction to the PCI-based fabric.
16. The computing device of claim 13 , wherein the second fabric is further configured to convert a non-posted memory write transaction into a posted transaction and forward the posted transaction to the fabric-to-fabric bridge.
17. The computing device of claim 13 , wherein the fabric-to-fabric bridge is further configured to push posted memory writes from the second fabric to ensure read completion from the second fabric.
18. The computing device of claim 13 , wherein the SoC comprises at least one ARM-based processor core operatively coupled to the second fabric, and the communication chip comprises a PCI Express (PCIe) device coupled to the communication interface via a PCIe link.
19. The computing device of claim 18 , wherein the communication chip comprises a wireless communications chip.
20. A method, comprising
originating a write memory transaction from a first component operatively coupled to a first fabric comprising a Peripheral Component Interconnect (PCI)-based fabric, a first write memory transaction comprising a posted memory write transaction and being targeted to a second component operatively coupled to a second fabric comprising one of an Open Core Protocol (OCP) or an Advanced Microcontroller Bus Architecture (AMBA)-based fabric that is coupled to the first fabric via a fabric-to-fabric bridge; and
at the fabric-to-fabric bridge, converting the posted memory write transaction into a non-posted memory write transaction and serializing the non-posted memory write transaction while forwarding the transaction towards the second fabric.
21. The method of claim 20 , further comprising:
serializing read returns towards the second fabric, wherein the fabric-to-fabric bridge does not return read data to the second fabric until a previous non-posted write towards the first fabric completes.
22. The method of claim 20 , further comprising:
creating a programmable window in system memory space accessible to the fabric-to-fabric bridge; and
streaming and/or pipelining memory writes as posted transactions via the programmable window.
23. The method of claim 20 , further comprising:
converting, at the fabric-to-fabric bridge, a non-posted memory write transaction originating from a second component operatively coupled to the second fabric into a posted transaction and forwarding the posted transaction to the first fabric.
24. The method of claim 20 , further comprising:
converting, at the second fabric, a non-posted memory write transaction originating from a second component operatively coupled to the second fabric into a posted transaction and forwarding the posted transaction to the fabric-to-fabric bridge.
25. The method of claim 20 , wherein the method is implemented on a System on a Chip (SoC) comprising at least one ARM-based processor core operatively coupled to the second fabric.
26. An apparatus comprising:
a first interconnect fabric to which a first plurality of Intellectual Property (IP) blocks are coupled, wherein the first interconnect fabric is configured to support posted memory write transactions;
a second interconnect fabric to which a second plurality of IP blocks are coupled, wherein the second interconnect fabric is configured to support non-posted memory write transactions; and
a fabric-to-fabric bridge configured to:
facilitate transfer of information between the first interconnect fabric and the second interconnect,
convert a posted memory write transaction from the first interconnect fabric into a non-posted memory write transaction, and
serialize the non-posted memory write transaction upon sending the transaction towards the second interconnect fabric.
27. The apparatus of claim 26 , wherein the fabric-to-fabric bridge is further configured to serialize read returns towards the second fabric, wherein the fabric-to-fabric bridge does not return read data to the second fabric until a previous non-posted write towards the first fabric completes.
28. The apparatus of claim 26 , wherein the fabric-to-fabric bridge is further configured to convert a non-posted memory write transaction into a posted transaction and forward the posted transaction to the first fabric.
29. The apparatus of claim 26 , wherein the fabric-to-fabric bridge is further configured to push posted memory writes from the second fabric to ensure read completion from the second fabric.
30. The apparatus of claim 26 , wherein the fabric-to-fabric bridge includes:
a first First-in First out (FIFO) buffer comprising a downward command queue; and
a second FIFO buffer comprising a downward data queue.
31. The apparatus of claim 30 , wherein the fabric-to-fabric bridge includes:
a third FIFO buffer comprising an upward command queue; and
a fourth FIFO buffer comprising an upward data queue.
32. The apparatus of claim 31 , wherein the fabric-to-fabric bridge further comprises a clock crossing domain.
33. The apparatus of claim 26 , wherein the second fabric comprises an Advanced Microcontroller Bus Architecture (AMBA)-based fabric to which at least one ARM-based processor core is operatively coupled.
34. The apparatus of claim 26 , wherein the first fabric comprises a Peripheral Component Interconnect (PCI)-based fabric, further comprising at least one x86-based processor core operatively coupled to the first fabric.
35. The apparatus of claim 34 , wherein the apparatus further comprises:
a coherent fabric to which a plurality of x86-based processor cores are coupled; and
a bridge, coupled between the PCI-based fabric and the coherent fabric.
36. The apparatus of claim 26 , wherein the second fabric comprises one of an Open Core Protocol (OCP) fabric or an Advanced Microcontroller Bus Architecture (AMBA)-based fabric, further comprising a third fabric coupled to the second fabric, the third fabric comprising one of a secondary OCP fabric or a secondary AMBA-based fabric.
37. The apparatus of claim 26 , wherein the second fabric comprises an Open Core Protocol (OCP) fabric and the apparatus comprises:
a PCI ordering domain;
a First-in First-out (FIFO) ordering domain; and
an OCP ordering domain.