Patent Application
App. No. 11/141,993
Context scheduling
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Abstract
A programmable processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, fetch logic for determining an address of an instruction, with the fetch logic including scheduling logic that schedules execution of the instruction contexts based on condition signals indicating an availability of a hardware resource, with the condition signals being divided into groups of condition signals, which are sampled in turn by the scheduling logic to provide a plurality of scan sets of sampled conditions.
Claims (1)
1 . A device and/or method substantially as shown and described.
Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Oct 20, 2005
From: WISHNEUSKY, JOHN A.
To: INTEL CORPORATION
Reel/Frame 017103/0437 →