Memory device, circuits and methods for operating a memory device
View Patent ↗A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.
1. A ferroelectric memory device comprising:
a plurality of bitlines;
a sense amplifier to sense a signal of a select bitline of the plurality relative to that of a reference bitline of the plurality;
an amplifier to source the sense amplifier with a reference signal representative of that of the reference bitline; and
a read controller responsive to a read request to isolate the reference bitline from a voltage source.
2. A device according to claim 1 , further comprising:
a plurality of wordlines;
an active wordline of the plurality crossing the active bitline and the reference bitline with ferroelectric material therebetween;
a first voltage source to provide a read level voltage for biasing the active wordline; and
a second voltage source to provide a quiescent level voltage for biasing wordlines of the plurality other than the active wordline;
at least one of the first and second voltage sources comprising a supply switch electrically disposed in the serial path associated with the supply of respective read level or quiescent level voltages.
3. A device according to claim 2 , in which the at least one of the first and second voltage sources further comprises a capacitor electrically coupled to the serial path on a side of the supply switch opposite the supply.
4. A device according to claim 3 , in which the capacitor comprises at least one of a doped-well in a semiconductor substrate and insulated gate of a drain-source shorted MOSFET formed within the semiconductor substrate.
5. A device according to claim 4 , in which the plurality of wordlines and bitlines of the ferroelectric memory device form an array of ferroelectric memory cells, the array of ferroelectric memory cells disposed over at least a portion of the doped-well of the semiconductor substrate.
6. A device according to claim 5 , in which the supply switch is disposed on the semiconductor substrate.
7. A device according to claim 2 , in which
the supply switch comprises at least one MOSFET having its channel disposed between the plurality of wordlines and the supply; and
the read controller to drive the gate of the at least one MOSFET responsive to the read request.
8. A device according to claim 2 , in which
the supply switch comprises first and second MOSFETs having channels coupled in parallel with each other, the parallel channels together within the serial path to the supply; and
the read controller to drive the gates of the first and second MOSFETs separately.
9. A device according to claim 1 , in which the switch comprises a MOSFET having its channel electrically disposed in series with an electrical path between the reference bitline and the reference voltage source.