Transistor gate electrode having conductor material layer
View Patent ↗Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
1. An apparatus comprising:
a transistor device channel comprising a silicon germanium (SiGe) material on a circuit substrate;
a gate dielectric for the transistor device, the gate dielectric comprising a material having a dielectric constant greater than a dielectric constant of silicon dioxide; and
a gate electrode over the gate dielectric, the gate electrode comprising a conductor material and a layer of semiconductor material over the conductor material, wherein the conductor material comprises one of a titanium nitride (TiN), a tantalum nitride (TaN), and a silicide, and wherein the semiconductor material of the gate electrode is a P-type gate electrode having an electrically positive charge.
2. The apparatus of claim 1 , wherein a hydrostatic pressure compressive strain is induced in the SiGe material by a lattice spacing of the circuit substrate material being smaller than a lattice spacing of at least one junction region.
3. The apparatus of claim 2 , wherein the substrate is silicon (Si), and wherein a bi-axial compressive strain in the channel is caused by a lattice spacing of the SiGe material being larger than a lattice spacing of the substrate material defining an interface surface of the substrate.
4. The apparatus of claim 1 , wherein the channel is a layer of a Si 1-Y Ge Y material on an area of a Si 1-X Ge X material defining an interface surface of a substrate of graded relaxed silicon germanium material;
wherein the layer of Si 1-Y Ge Y material is under a compressive strain caused by a lattice spacing of the Si 1-Y Ge Y material being larger than a lattice spacing of the Si 1-X Ge X material at the interface surface.
5. The apparatus of claim 4 , wherein X is in a range between 0.1 and 0.3 at the interface surface, and Y is greater than X by a range between 0.1 and 0.3.
6. The apparatus of claim 1 , wherein the SiGe material of the channel comprises a selective chemical vapor deposition (CVD) epitaxial blanket growth of compressive strained SiGe material.
7. The apparatus of claim 1 , wherein the conductor material of the gate electrode has a work function between 4.4 electron volts and 4.7 electron volts with respect to silicon.
8. The apparatus of claim 7 , further comprising a first junction region and a second junction region in the channel adjacent to the gate electrode, wherein the first junction region and the second junction region include a sufficient thickness of SiGe material having a larger lattice spacing than a lattice spacing of the substrate material to cause a compressive strain in the channel in a range of between 0.5% compression and 2.5% compression.
9. An apparatus comprising:
a transistor device channel comprising a silicon germanium (SiGe) material on a circuit substrate;
a gate dielectric for the transistor device, the gate dielectric comprising a material having a dielectric constant greater than a dielectric constant of silicon dioxide, the gate dielectric comprising HfO; and
a gate electrode over the gate dielectric, the gate electrode comprising a conductor material having a work function in a range between a valence energy band edge and a conduction energy band edge for silicon (Si), the gate electrode further comprising a layer of semiconductor material over the conductor material, wherein the semiconductor material of the gate electrode is a P-type gate electrode having an electrically positive charge.
10. The apparatus of claim 9 , wherein a hydrostatic pressure compressive strain is induced in the SiGe material by a lattice spacing of the circuit substrate material being smaller than a lattice spacing of at least one junction region.
11. The apparatus of claim 10 , wherein the substrate is silicon (Si), and wherein the compressive strain is a bi-axial compressive strain in the channel caused by a lattice spacing of the SiGe material being larger than a lattice spacing of the substrate material defining an interface surface of the substrate.
12. The apparatus of claim 9 , wherein the conductor material of the gate electrode comprises one of a titanium nitride (TiN), a tantalum nitride (TaN), and a silicide; and wherein the work function is between 4.4 electron volts and 4.7 electron volts with respect to silicon.
13. The apparatus of claim 12 , further comprising a first junction region and a second junction region in the channel adjacent to the gate electrode, wherein the first junction region and the second junction region include a sufficient thickness of SiGe material having a larger lattice spacing than a lattice spacing of the substrate material to cause a compressive strain in the channel in a range of between 0.5% compression and 2.5% compression.
14. The apparatus of claim 9 , wherein the gate electrode has a thickness of between 10 and 20 angstroms of conductor material to relieve electron depletion effects at an interface between the gate electrode and the gate dielectric, and to cause the transistor to have a threshold “ON” voltage of between 0.2 volts and 0.3 volts.
15. An apparatus comprising:
a transistor device channel comprising a silicon germanium (SiGe) material on a circuit substrate;
a gate dielectric for the transistor device, the gate dielectric comprising a material having a dielectric constant greater than a dielectric constant of silicon dioxide; and
a P-type gate electrode having an electrically positive charge over the gate dielectric, the gate electrode comprising a conductor material, the gate electrode further comprising a layer of semiconductor material over the conductor material.
16. The apparatus of claim 15 , wherein the gate dielectric comprises HfO.
17. The apparatus of claim 15 , wherein the conductor material of the gate electrode comprises one of a titanium nitride (TiN), a tantalum nitride (TaN), and a silicide.
18. The apparatus of claim 15 , wherein the conductor material of the gate electrode has a work function between 4.4 electron volts and 4.7 electron volts with respect to silicon.
19. An apparatus comprising:
an N-type PMOS transistor device channel comprising a layer of compressive strained silicon germanium material on a first area of a substrate material defining a first interface surface of a CMOS circuit substrate;
a gate dielectric for the PMOS transistor device, the gate dielectric having a dielectric constant greater than a dielectric constant of silicon dioxide;
a gate electrode for the PMOS transistor device over the gate dielectric for the PMOS transistor device, the gate electrode for the PMOS transistor device comprising a P-type semiconductor material on a conductor material that comprises one of a titanium nitride (TiN), a tantalum nitride (TaN), and a silicide;
a P-type first junction region and a P-type second junction region in the N-type PMOS channel adjacent the gate electrode for the PMOS transistor device.
20. The apparatus of claim 19 , further comprising:
a P-type NMOS transistor device channel on a second area of the substrate material defining a different second interface surface of the CMOS circuit substrate separated from the first interface surface by an electronically insulating material;
a gate dielectric for the NMOS transistor device;
an N-type gate electrode for the NMOS transistor device over the gate dielectric for the NMOS transistor device;
an N-type first junction region and an N-type second junction region in the P-type NMOS channel adjacent the N-type gate electrode for the NMOS transistor device.
21. The apparatus of claim 19 , wherein the PMOS transistor has a threshold “ON” voltage of between 0.2 volts and 0.3 volts, and wherein the substrate is a layer of graded relaxed silicon germanium material having a grading concentration of germanium that increases from 0 percent to between 10 percent and 30 percent at the first interface surface.
22. An apparatus comprising:
an N-type PMOS transistor device channel comprising a layer of compressive strained silicon germanium material on a first area of a substrate material defining a first interface surface of a CMOS circuit substrate;
a gate dielectric for the PMOS transistor device, the gate dielectric having a dielectric constant greater than a dielectric constant of silicon dioxide;
a gate electrode for the PMOS transistor device over the gate dielectric for the PMOS transistor device, the gate electrode for the PMOS transistor device comprising a P-type semiconductor material on a conductor material having a work function between 4.4 electron volts and 4.7 electron volts with respect to silicon;
a P-type first junction region and a P-type second junction region in the N-type PMOS channel adjacent the gate electrode for the PMOS transistor device.
23. The apparatus of claim 22 , further comprising:
a P-type NMOS transistor device channel on a second area of the substrate material defining a different second interface surface of the CMOS circuit substrate separated from the first interface surface by an electronically insulating material;
a gate dielectric for the NMOS transistor device;
an N-type gate electrode for the NMOS transistor device over the gate dielectric for the NMOS transistor device;
an N-type first junction region and an N-type second junction region in the P-type NMOS channel adjacent the N-type gate electrode for the NMOS transistor device.
24. The apparatus of claim 22 , wherein the PMOS transistor has a threshold “ON” voltage of between 0.2 volts and 0.3 volts, and wherein the substrate is a layer of graded relaxed silicon germanium material having a grading concentration of germanium that increases from 0 percent to between 10 percent and 30 percent at the first interface surface.