IP Library Granted Patent US 9,627,029
Granted Patent B2
US 9,627,029 · App. 14/639,025 · Granted Apr 18, 2017

Method for training a control signal based on a strobe signal in a memory module

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,627,029
App. No.
14/639,025
Granted
Apr 18, 2017
Kind
B2
Abstract

A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.

Claims (22)

1. A method, comprising:

transmitting, by a memory controller, a chip select signal and a clock signal to a memory module; and

determining adjustments to the chip select signal with respect to the clock signal, by iteratively analyzing a strobe signal received by the memory controller from the memory module.

2. The method of claim 1 , wherein the memory controller continuously transmits the clock signal to the memory module.

3. The method of claim 1 , wherein the adjustments to the chip select signal with respect to the clock signal are determined by the memory controller.

4. A memory controller coupled to a memory module, wherein the memory controller is operable to:

transmit a chip select signal and a clock signal to the memory module; and

determine adjustments to the chip select signal with respect to the clock signal, by iteratively analyzing a strobe signal received by the memory controller from the memory module.

5. The memory controller of claim 4 , wherein the memory controller continuously transmits the clock signal to the memory module.

6. A computational system, comprising:

a memory module;

a memory controller coupled to the memory module; and

a processor coupled to the memory controller, wherein the processor is operable to:

transmit a chip select signal and a clock signal to the memory module; and

determine adjustments to the chip select signal with respect to the clock signal, by iteratively analyzing a strobe signal received by the memory controller from the memory module.

7. The computational system of claim 6 , wherein the memory controller continuously transmits the clock signal to the memory module.

8. A system, comprising:

a memory module; and

a memory controller coupled to a memory module, where the memory controller is operable to:

transmit a chip select signal and a clock signal to the memory module; and

determine adjustments to the chip select signal with respect to the clock signal, by iteratively analyzing a strobe signal received by the memory controller from the memory module.

9. The system of claim 8 , wherein the memory controller continuously transmits the clock signal to the memory module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →