Low power universal serial bus
View Patent ↗Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.
1. A universal serial bus apparatus, comprising:
a physical layer, comprising;
a first signal line eD+;
a second signal line eD−;
a single-ended driver enable SE_Driver_Enable;
a single-ended receiver enable SE_Receiver_Enable;
a first Low-speed/Full-speed transmitter having a single-ended driver input SE_Driver_Input_P, an input coupled to the single-ended driver enable SE_Driver_Enable, and an output coupled to the first signal line eD+;
a second Low-speed/Full-speed transmitter having a single-ended driver input SE_Driver_Input_N, an input coupled to the single-ended driver enable SE_Driver_Enable, and an output to be coupled to the second signal line eD−;
a first Low-speed/Full-speed receiver having an input coupled to the first signal line eD+, an input coupled to the single-ended receiver enable SE_Receiver_Enable, and an output coupled to a single-ended receiver output SE_Receiver_Output_P;
a second Low-speed/Full-speed receiver having an input coupled to the second signal line eD−, an input coupled to the single-ended receiver enable SE_Receiver_Enable, and an output coupled to a single-ended receiver output SE_Receiver_Output_N;
a first pull-down resistor Rpd having a first terminal coupled to the first signal line eD+ and a second terminal; and
a second pull-down resistor Rpd having a first terminal coupled to the second signal line eD− and a second terminal coupled to the second terminal of the first pull-down resistor.
2. The universal serial bus apparatus of claim 1 , wherein the first Low-speed/Full-speed transmitter, the second Low-speed/Full-speed transmitter, the first Low-speed/Full-speed receiver, and the second Low-speed/Full-speed receiver comprise single-ended digital CMOS components configured for 1 volt signaling.
3. The universal serial bus apparatus of claim 1 , wherein the first Low-speed/Full-speed transmitter, the second Low-speed/Full-speed transmitter, the first Low-speed/Full-speed receiver, and the second Low-speed/Full-speed receiver are to use 1 volt signaling.
4. The universal serial bus apparatus of claim 1 , (New) The universal serial bus apparatus of claim 1 , wherein the first Low-speed/Full-speed transmitter, the second Low-speed/Full-speed transmitter, the first Low-speed/Full-speed receiver, and the second Low-speed/Full-speed receiver are to use 1 volt CMOS circuitry.
5. The universal serial bus apparatus of claim 1 , wherein the first Low-speed/Full-speed transmitter, the second Low-speed/Full-speed transmitter, the first Low-speed/Full-speed receiver, and the second Low-speed/Full-speed receiver comprise digital CMOS components.
6. The universal serial bus apparatus of claim 1 , the physical layer further comprising a high speed transceiver to transmit data to and to receive data from the first signal line eD+ and the second signal line eD− using differential signaling.
7. The universal serial bus apparatus of claim 6 , wherein the high speed transceiver includes a High-speed transmitter and a High-speed receiver.
8. The universal serial bus apparatus of claim 6 , wherein the high speed transceiver is to use 0.2 volt differential signaling.
9. The universal serial bus apparatus of claim 6 , wherein the high speed transceiver is an analog transceiver for low swing differential signaling.
10. The universal serial bus apparatus of claim 6 , wherein the high speed transceiver includes a squelch detector.
11. The universal serial bus apparatus of claim 6 , the high speed transceiver including a transmitter to implement source termination.
12. The universal serial bus apparatus of claim 6 , the high speed transceiver including a receiver to implement receiver termination.
13. The universal serial bus apparatus of claim 1 , wherein the physical layer is configured to use single-ended communications while operating in a Low-speed/Full-speed mode and is configured to use differential signaling while operating in a high speed mode.
14. The universal serial bus apparatus of claim 6 , wherein the physical layer is configured to use single-ended communications while operating in a Low-speed/Full-speed mode and is configured to use differential signaling while operating in a high speed mode.
15. The universal serial bus apparatus of claim 1 , further comprising a repeater to convert received signals on signal line eD+ and on signal line eD− into USB2 compatible signals.
16. The universal serial bus apparatus of claim 1 , wherein the universal serial bus apparatus is to receive a digital ping that indicates a device presence.
17. The universal serial bus apparatus of claim 1 , wherein the universal serial bus apparatus is to detect device disconnect if it does not receive a digital ping from an other device within a specific time period.
18. The universal serial bus apparatus of claim 1 , wherein the first pull-down resistor Rpd and the second pull-down resistor Rpd are to hold a bus to ground during power-up or when a link is idle.
19. The universal serial bus apparatus of claim 1 , further comprising a link layer and a protocol layer.
20. A universal serial bus apparatus, comprising:
a physical layer, comprising;
a pair of Low-speed/Full-speed transmitters to be coupled to a pair of signal lines and to transmit data to the pair of signal lines using single-ended digital communication; and
a pair of Low-speed/Full-speed receivers to be coupled to the pair of signal lines and to receive data from the pair of signal lines using single-ended digital communication
a pair of pull-down resistors selectively coupled to the pair of signal lines, the pair of pull-down resistors to couple both of the pair of signal lines to ground during an idle state.
21. The universal serial bus apparatus of claim 20 , wherein the pair of Low-speed/Full-speed transmitters and the pair of Low-speed/Full-speed receivers comprise single-ended digital CMOS components configured for 1 volt signaling.
22. The universal serial bus apparatus of claim 20 , wherein the pair of Low-speed/Full-speed transmitters and the pair of Low-speed/Full-speed receivers are to use 1 volt signaling.
23. The universal serial bus apparatus of claim 20 , wherein the pair of Low-speed/Full-speed transmitters and the pair of Low-speed/Full-speed receivers are to use 1 volt CMOS circuitry.
24. The universal serial bus apparatus of claim 20 , wherein the pair of Low-speed/Full-speed transmitters and the pair of Low-speed/Full-speed receivers comprise digital CMOS components.
25. The universal serial bus apparatus of claim 20 , the physical layer further comprising a high speed transceiver to transmit data to and to receive data from the pair of signal lines using differential signaling.
26. The universal serial bus apparatus of claim 25 , wherein the high speed transceiver includes a High-speed transmitter and a High-speed receiver.
27. The universal serial bus apparatus of claim 25 , wherein the high speed transceiver is to use 0.2 volt differential signaling.
28. The universal serial bus apparatus of claim 25 , wherein the high speed transceiver is an analog transceiver for low swing differential signaling.
29. The universal serial bus apparatus of claim 25 , wherein the high speed transceiver includes a squelch detector.
30. The universal serial bus apparatus of claim 25 , the high speed transceiver including a transmitter to implement source termination.
31. The universal serial bus apparatus of claim 25 , the high speed transceiver including a receiver to implement receiver termination.
32. The universal serial bus apparatus of claim 20 , wherein the physical layer is configured to use single-ended communications while operating in a Low-speed/Full-speed mode and is configured to use differential signaling while operating in a high speed mode.
33. The universal serial bus apparatus of claim 25 , wherein the physical layer is configured to use single-ended communications while operating in a Low-speed/Full-speed mode and is configured to use differential signaling while operating in a high speed mode.
34. The universal serial bus apparatus of claim 20 , further comprising a repeater to convert received signals into USB2 compatible signals.
35. The universal serial bus apparatus of claim 20 , wherein the universal serial bus apparatus is to receive a digital ping that indicates a device presence.
36. The universal serial bus apparatus of claim 20 , wherein the universal serial bus apparatus is to detect device disconnect if it does not receive a digital ping from an other device within a specific time period.
37. The universal serial bus apparatus of claim 20 , further comprising two pull-down resistors to hold a bus to ground during power-up or when a link is idle.
38. The universal serial bus apparatus of claim 20 , further comprising a link layer and a protocol layer.