Bandgap reference circuit with low output impedance stage and power-on detector
View Patent ↗Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.
1. An apparatus comprising:
a bandgap core to provide a control signal; and
an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at a first output node, wherein the first output node is coupled to the bandgap core and the output stage comprises an n-type driver coupled to the first output node, and a negative feedback loop coupled to the n-type output driver.
2. The apparatus of claim 1 , wherein the bandgap core is a resistor-based bandgap.
3. The apparatus of claim 2 , wherein the first output node is a temperature independent bandgap reference.
4. The apparatus of claim 1 further comprises:
a power-on detector coupled to the output stage, the power-on detector having a second output node.
5. The apparatus of claim 4 , wherein the power-on detector to compare a current of the output stage with a reference current to generate a power-on detect signal at the second output node of the power-on detector.
6. The apparatus of claim 4 , wherein the power-on detector comprises:
an n-type transistor to mirror current of the output stage; and
a p-type transistor coupled in series with the n-type transistor, the p-type transistor to be biased by a bias signal, and wherein a node common between the n-type transistor and the p-type transistor is coupled to the second output node of the power-on detector.
7. The apparatus of claim 1 , wherein the negative feedback loop includes a p-type source follower.
8. The apparatus of claim 7 , wherein the negative feedback loop includes:
a current source; and
a current mirror coupled to the p-type source follower and the current source.
9. The apparatus of claim 8 , wherein the output driver has a gate terminal coupled to the current source and the current mirror.
10. The apparatus of claim 1 , wherein the first output node is coupled to a power supply node to provide power supply to various devices of the bandgap core.
11. The apparatus of claim 1 , wherein the output stage comprises:
a p-type source follower to receive the control signal from the bandgap core; and
an n-type driver coupled in series to the p-type source follower, and wherein a common coupling node of the n-type driver and the p-type source follower forms the first output node.
12. The apparatus of claim 11 , wherein the common coupling node is at source terminals of the p-type source follower and the n-type driver, and wherein current in the p-type source follower is sampled and fed back by a negative feedback loop to a gate terminal of the n-type driver.
13. The apparatus of claim 12 further comprises a power on detector to sample the current in the p-type source follower and to compare the current to a reference current to produce a signal on a second output node.
14. The apparatus of claim 11 , wherein the first output node is a power supply node of at least one circuit element in the bandgap core.
15. The apparatus of claim 11 , wherein the output stage comprises a capacitor coupled to a gate terminal of the n-type driver.
16. The apparatus of claim 11 , wherein the output stage comprises:
an n-type diode connected transistor coupled in series of the p-type source follower;
a first n-type transistor with a gate terminal coupled to a gate terminal of the n-type diode connected transistor; and
a p-type current source controllable by a bias signal, the p-type current source coupled in series with the first n-type transistor.
17. The apparatus of claim 16 further comprises:
a power-on detector with a second output node and a second n-type transistor with a gate terminal coupled to a gate terminal of the first n-type transistor of the output stage, wherein a drain terminal of the second n-type transistor is coupled to the second output node, wherein the power-on-detector comprises a current source coupled to the second output node.
18. A system comprising:
a memory unit;
a processor, coupled to the memory unit, the processor including
a bandgap core to provide a control signal; and
an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at a first output node, wherein the first output node is coupled to the bandgap core and the output stage comprises an n-type output driver coupled to the first output node, and a negative feedback loop coupled to the n-type output driver; and
a wireless interface for allowing the processor to communicate with another device; and
a display unit.
19. A system comprising:
a voltage regulator which includes:
a bandgap core to provide a control signal; and
an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at a first output node, wherein the first output node is coupled to the bandgap core and the output stage comprises a n-type output driver coupled to the first output node, and a negative feedback loop coupled to the n-type output driver;
a processor coupled to the voltage regulator; and
a wireless interface for allowing the processor to communicate with another device.