Integrating n-type and p-type metal gate transistors
View Patent ↗At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
1. A process comprising:
forming an n-type and a p-type transistor upon a semiconductor substrate, the n-type and p-type transistors comprising n-type and p-type polysilicon gates, respectively;
forming an interlayer dielectric layer on a top of the n-type and p-type transistors;
removing an interlayer dielectric (ILDO) layer from the top of the n-type and p-type polysilicon gates;
etching the n-type polysilicon gate to form a first trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on a bottom of the first trench;
depositing n-type metal into the first trench;
removing excess n-type gate material to expose a top of the n-type metal gate and the p-type polysilicon gate;
etching the p-type polysilicon gate to form a second trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on a bottom of the second trench;
depositing a p-type metal gate within the second trench; and
removing excess p-type gate material to expose the top of the n-type metal gate and the p-type metal gate.
2. The process of claim 1 further comprising forming the ILD0 layer on the top of the n-type and p-type transistors.
3. The process of claim 2 further comprising forming source, gate, and drain contacts to the n-type and p-type transistors.
4. The process of claim 1 wherein the n-type metal gate is selected from a group consisting of Hf, Zr, Ti, Ta, and Al.
5. The process of claim 1 wherein the p-type metal gate is selected from a group consisting of Ru, Pd, Pt, Co, Ni, TiAlN and WCN.
6. The process of claim 1 wherein the p-type metal gate and the n-type metal gate is at least 50 angstroms and no greater than 1000 angstroms thick.
7. The process of claim 1 wherein etching the n-type and p-type polysilicon gates is an ammonium hydroxide etch.
8. The process of claim 1 wherein etching the n-type and p-type polysilicon gates is performed by using a wet etch.
9. The process of claim 1 wherein the n-type metal gate is doped by implanting n-type material after the n-type metal gate has been deposited into the first trench.
10. The process of claim 1 wherein the p-type metal gate is doped by implanting the metal gate with p-type material after the p-type metal gate has been deposited into the second trench.
11. A process comprising:
forming an n-type and a p-type transistor upon a semiconductor substrate, the n-type and p-type transistors comprising n-type and p-type polysilicon gates, respectively;
removing an n-type polysilicon gate from a n-type transistor formed on a semiconductor substrate to form a first trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on a bottom of the first trench, while maintaining a p-type polysilicon gate of a p-type transistor formed on the semiconductor substrate;
depositing n-type metal into the first trench to form a n-type metal gate and removing excess n-type metal to expose a top of the n-type metal gate and the p-type polysilicon gate;
removing the p-type polysilicon gate to form a second trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on a bottom of the second tench; and
depositing p-type metal into the second trench to form a p-type metal gate and removing excess p-type metal to expose the top of the n-type metal gate and the p-type metal gate.
12. The process of claim 11 further comprising removing an interlayer dielectric layer from a top of the n-type and p-type polysilicon gates.
13. The process of claim 11 further comprising forming source, gate, and drain contacts to the n-type and p-type transistors.