Method and apparatus for optimizing strobe to clock relationship
View Patent ↗To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.
1. A method for synchronizing a strobe signal to a clock signal relationship for a memory comprising:
a memory controller to send the clock signal and the strobe signal to a memory device;
the memory device to sample the clock signal with the strobe signal;
the memory device to send back information asynchronously on one or more data pins; and
the memory controller advancing the strobe signal if a binary zero value is read and the memory controller retarding the strobe signal if a binary one value is read.
2. The method of claim 1 wherein the memory device is a DDR3 DRAM.
3. The method of claim 1 wherein the data pins are DQ pins.
4. A method for synchronizing a strobe signal to a clock signal relationship for a memory comprising:
sending the clock signal and the strobe signal to a memory device;
sampling the clock signal with the strobe signal;
sending back information asynchronously on one or more data pins; and
advancing the strobe signal if a binary zero value is read or retarding the strobe signal if a binary one value is read.
5. The method of claim 4 wherein the memory device is a DDR3 DRAM.
6. The method of claim 4 wherein the data pins are DQ pins.
7. A method for synchronizing a strobe signal to a clock signal relationship for a memory while the memory device is in a test mode of operation comprising:
sending the clock signal and the strobe signal to a memory device;
sampling the clock signal with the strobe signal;
sending back information asynchronously on one or more data pins; and
advancing the strobe signal if a binary zero value is read or retarding the strobe signal if a binary one value is read.
8. The method of claim 7 wherein the memory device is a DDR3 DRAM.
9. The method of claim 7 wherein the data pins are DQ pins.
10. A system to synchronize a strobe signal to a clock signal relationship for a memory comprising:
a memory controller to send the clock signal and the strobe signal to a memory device;
the memory device to sample the clock signal with the strobe signal;
the memory device to send back information asynchronously on one or more data pins; and
the memory controller advancing the strobe signal if a binary zero value is read and the memory controller retarding the strobe signal if a binary one value is read.
11. The method of claim 10 wherein the memory device is a DDR3 DRAM.
12. The method of claim 10 wherein the data pins are DQ pins.